PT
STA (6+ Years) Bengaluru
Accepting applicationsPozibility Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Senior ASICDFTFPGAPerlPython
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Senior
Country
India
Company Description Pozibility Technologies Pvt Ltd is a design services company founded by leaders with over 18 years of experience in ASIC design services and embedded software development. The company enables customers with end-to-end IC design, embedded software, software testing, and system design solutions through a motivated team of skilled engineers. Expertise spans ASIC/SoC architecture design, RTL coding and verification, FPGA design and prototyping, synthesis and STA, formal verification, DFT, physical design, and analog mixed-signal design and layout. The embedded team covers pre-silicon development through boot loaders, device drivers, and hardware abstraction layers, while the testing services team ensures products and applications meet stringent quality, business, and market expectations. Pozibility offers a technology-driven environment focused on high-quality engineering solutions and continuous learning.
Role Description This is a full-time, on-site STA (Static Timing Analysis) Engineer role based in Bengaluru. The STA engineer will perform block-level and full-chip timing analysis, including constraint development, timing closure, and sign-off across multiple process, voltage, and temperature corners. Day-to-day responsibilities include collaborating with front-end and physical design teams, reviewing synthesis and place-and-route outputs, debugging timing violations, and proposing optimization strategies. The role involves preparing STA reports, documenting methodologies, supporting design reviews, and ensuring designs meet performance, power, and reliability requirements. The engineer will also contribute to flow improvements, automation scripts, and best practices to enhance timing analysis efficiency and quality.
Qualifications
Strong STA skills including timing constraint development, timing closure, and sign-off using industry-standard tools such as PrimeTime or equivalent.
Solid understanding of ASIC/SoC design fundamentals, including RTL concepts, synthesis, and interaction with physical design flows.
Experience with multi-corner, multi-mode analysis, clock tree concepts, ECO implementation, and timing correlation across tools.
Proficiency with scripting languages (e.g., Tcl, Perl, Python) to automate STA flows, report generation, and data analysis.
Good grasp of signal integrity, OCV/AOCV/POCV, power-performance-area trade-offs, and design-for-test considerations as they relate to timing.
Ability to interpret specifications, collaborate with cross-functional teams, and communicate timing risks and mitigation plans clearly.
6+ years of relevant industry experience in STA or closely related ASIC/SoC implementation roles.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related technical field.
Experience working with complex SoCs, advanced technology nodes, and global engineering teams is an advantage.
Strong analytical mindset, attention
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Role Description This is a full-time, on-site STA (Static Timing Analysis) Engineer role based in Bengaluru. The STA engineer will perform block-level and full-chip timing analysis, including constraint development, timing closure, and sign-off across multiple process, voltage, and temperature corners. Day-to-day responsibilities include collaborating with front-end and physical design teams, reviewing synthesis and place-and-route outputs, debugging timing violations, and proposing optimization strategies. The role involves preparing STA reports, documenting methodologies, supporting design reviews, and ensuring designs meet performance, power, and reliability requirements. The engineer will also contribute to flow improvements, automation scripts, and best practices to enhance timing analysis efficiency and quality.
Qualifications
Strong STA skills including timing constraint development, timing closure, and sign-off using industry-standard tools such as PrimeTime or equivalent.
Solid understanding of ASIC/SoC design fundamentals, including RTL concepts, synthesis, and interaction with physical design flows.
Experience with multi-corner, multi-mode analysis, clock tree concepts, ECO implementation, and timing correlation across tools.
Proficiency with scripting languages (e.g., Tcl, Perl, Python) to automate STA flows, report generation, and data analysis.
Good grasp of signal integrity, OCV/AOCV/POCV, power-performance-area trade-offs, and design-for-test considerations as they relate to timing.
Ability to interpret specifications, collaborate with cross-functional teams, and communicate timing risks and mitigation plans clearly.
6+ years of relevant industry experience in STA or closely related ASIC/SoC implementation roles.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related technical field.
Experience working with complex SoCs, advanced technology nodes, and global engineering teams is an advantage.
Strong analytical mindset, attention
Show more Show less