STA - 5+ Years - Bangalore Location

Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise across the complete chip development lifecycle. Founded in 2018, the company has become a trusted partner for global semiconductor organizations, delivering high-quality design services tailored to product-driven teams. With engineering teams across India and Canada, LeadIC provides capabilities spanning custom, memory and analog layout, mixed-signal circuit design, digital design, verification, physical design, STA, DFT, and IP characterization. The organization operates with a strong engineering culture built on ownership, quality-driven execution, and flexible partnership models that adapt to diverse technical and business needs. Long-term relationships with global semiconductor leaders reflect LeadIC’s reliability and commitment to accelerating silicon success.
Role Description This is a full-time, on-site STA role based in Bengaluru South for candidates with 5+ years of relevant experience. The role focuses on static timing analysis for complex ASIC/SoC designs, including developing and maintaining timing constraints, running STA at various design stages, and analyzing timing reports. The STA engineer will work closely with physical design, synthesis, and RTL teams to identify, debug, and resolve setup, hold, and other timing issues, driving closure across multiple corners and modes. Day-to-day responsibilities include collaborating on signoff flows, refining methodologies, supporting tape-out schedules, and ensuring timing quality and consistency in alignment with project requirements. The role also involves documenting best practices, participating in technical reviews, and mentoring junior engineers as needed.
Qualifications

Strong expertise in STA tools and flows (e.g., PrimeTime or equivalent), including constraint development, timing report analysis, and timing closure across multi-mode, multi-corner scenarios.
Solid understanding of ASIC/SoC design fundamentals, including RTL, synthesis, and physical design concepts such as clock tree, placement, routing, and signoff considerations.
Knowledge of timing-related methodologies (e.g., MCMM, on-chip variation, signal integrity impact on timing) and experience working with standard cell libraries and timing models.
Proficiency with scripting for automation (e.g., Python, Perl, or shell scripting) to streamline STA runs, report processing, and flow enhancements.
Experience collaborating with cross-functional teams (PD, DFT, verification) to debug timing issues and drive closure under aggressive schedules.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
Strong analytical and problem-solving abilities, attention to detail, and ability to document and communicate technical findings clearly.
Prior experience in product or service-based semiconductor environments; exposure to high-speed, low-power, or advanced-node designs is an advantage.
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