NT
SRAM Senior / Staff / Principal – Design & Layout Engineers
Accepting applicationsNextiCron Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceCalibreSynopsysVLSIVerilog
Estimated market salary
₹59-106 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Eda
Experience
Mid_senior
Country
India
#Hiring: Senior SRAM / Memory Compiler Design & Layout Engineers
NextiCron Technologies is expanding its SRAM and memory compiler development team. We are looking for experienced semiconductor professionals with strong expertise in memory circuit design, compiler development, and a good understanding of custom memory layout.
Locations: Bangalore, Noida, Hyderabad
Employment Type: Full-time
Work Mode: Flexible, based on project requirements
Responsibilities
Design and develop SRAM, ROM, and register file memory compilers.
Work on memory architecture, read and write paths, sensing circuits, assist techniques, control logic, and design margins.
Perform functional, timing, power, yield, and PVT analysis.
Support memory characterization and the generation of Liberty and Verilog models.
Contribute to memory compiler architecture, validation, and automation flows.
Collaborate with custom layout engineers on bitcells, peripheral circuits, array integration, parasitic effects, and physical implementation.
Review layout-dependent effects and support DRC, LVS, EM/IR, LEF, and GDS deliverables.
Provide technical guidance and support the execution of memory compiler development projects.
Required Qualifications
3–15 years of hands-on experience in SRAM, embedded memory, register file, ROM, or memory compiler development.
The position may be offered at the Senior, Staff, Principal, or Lead level, depending on the candidate’s experience and technical expertise.
Strong understanding of memory architecture, transistor-level circuit operation, design margins, and PVT variation.
Experience with memory characterization and deliverables such as Liberty and Verilog models.
Good understanding of SRAM bitcell and peripheral layout, array integration, parasitic effects, DRC, and LVS.
Hands-on experience with Cadence, Synopsys, Siemens EDA/Calibre, or equivalent semiconductor design tools.
Experience with advanced-node or foundry-based memory development is preferred.
Direct experience in custom memory layout would be an advantage.
NOTE: This opening is specifically for professionals with relevant experience in VLSI, semiconductor memory design, custom IC layout, memory characterization, or memory compiler development.
Applications from general electrical engineering, mechanical engineering, power systems, embedded systems, PCB design, manufacturing, or unrelated software backgrounds will not be considered
📩 Apply or Refer:
Send your CV to hr@nexticrontechnologies.com
#NextiCron #Hiring #VLSIJobs #SemiconductorJobs #SRAM #MemoryCompiler #MemoryDesign #CustomLayout #MemoryLayout #CircuitDesign #LayoutEngineer #DesignEngineer #StaffEngineer #PrincipalEngineer #BangaloreJobs #NoidaJobs #HyderabadJobs
Show more Show less
NextiCron Technologies is expanding its SRAM and memory compiler development team. We are looking for experienced semiconductor professionals with strong expertise in memory circuit design, compiler development, and a good understanding of custom memory layout.
Locations: Bangalore, Noida, Hyderabad
Employment Type: Full-time
Work Mode: Flexible, based on project requirements
Responsibilities
Design and develop SRAM, ROM, and register file memory compilers.
Work on memory architecture, read and write paths, sensing circuits, assist techniques, control logic, and design margins.
Perform functional, timing, power, yield, and PVT analysis.
Support memory characterization and the generation of Liberty and Verilog models.
Contribute to memory compiler architecture, validation, and automation flows.
Collaborate with custom layout engineers on bitcells, peripheral circuits, array integration, parasitic effects, and physical implementation.
Review layout-dependent effects and support DRC, LVS, EM/IR, LEF, and GDS deliverables.
Provide technical guidance and support the execution of memory compiler development projects.
Required Qualifications
3–15 years of hands-on experience in SRAM, embedded memory, register file, ROM, or memory compiler development.
The position may be offered at the Senior, Staff, Principal, or Lead level, depending on the candidate’s experience and technical expertise.
Strong understanding of memory architecture, transistor-level circuit operation, design margins, and PVT variation.
Experience with memory characterization and deliverables such as Liberty and Verilog models.
Good understanding of SRAM bitcell and peripheral layout, array integration, parasitic effects, DRC, and LVS.
Hands-on experience with Cadence, Synopsys, Siemens EDA/Calibre, or equivalent semiconductor design tools.
Experience with advanced-node or foundry-based memory development is preferred.
Direct experience in custom memory layout would be an advantage.
NOTE: This opening is specifically for professionals with relevant experience in VLSI, semiconductor memory design, custom IC layout, memory characterization, or memory compiler development.
Applications from general electrical engineering, mechanical engineering, power systems, embedded systems, PCB design, manufacturing, or unrelated software backgrounds will not be considered
📩 Apply or Refer:
Send your CV to hr@nexticrontechnologies.com
#NextiCron #Hiring #VLSIJobs #SemiconductorJobs #SRAM #MemoryCompiler #MemoryDesign #CustomLayout #MemoryLayout #CircuitDesign #LayoutEngineer #DesignEngineer #StaffEngineer #PrincipalEngineer #BangaloreJobs #NoidaJobs #HyderabadJobs
Show more Show less