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SRAM / Memory Design Engineer – Semiconductor Memory IP
Accepting applicationsBest NanoTech · Bengaluru, Karnataka, India
Full-Time Mid_senior SRAMMemory DesignTransistor-LevelCustom LayoutMemory IP
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
SRAM / Memory Design Engineer Semiconductor Memory IP
Location: Bengaluru, India
Work Mode: Onsite
Experience: 5 12 Years
Industry: Semiconductor / VLSI / ASIC Design
Role Overview
We are looking for an experienced SRAM / Memory Design Engineer to develop and optimize embedded memory IP solutions for advanced semiconductor technologies. The role involves SRAM architecture, transistor-level memory circuit design, memory compiler development, read/write optimization, low-power memory design, characterization, and silicon validation for high-performance SoC and ASIC products.
The successful candidate will work closely with Process Technology, Device Engineering, Physical Design, CAD, Product Engineering, and Verification teams to deliver robust, manufacturable memory solutions supporting AI, Automotive, Networking, Data Center, Industrial, and High-Performance Computing applications.
Key Responsibilities
Design and develop high-performance SRAM and embedded memory macros for advanced semiconductor process technologies.
Perform transistor-level memory circuit design, simulation, optimization, and verification.
Optimize read/write margins, stability, leakage power, access time, and memory yield across multiple PVT corners.
Design peripheral circuits including Sense Amplifiers, Write Drivers, Row Decoders, Column Decoders, Precharge Circuits, Wordline Drivers, and I/O circuitry.
Support memory compiler development and memory architecture optimization.
Perform SPICE simulations for functional verification, timing, power, noise, and reliability analysis.
Collaborate with Device, Process Integration, Physical Design, CAD, and Product Engineering teams throughout the design cycle.
Support memory characterization, silicon validation, yield improvement, and customer enablement.
Investigate silicon failures and perform root cause analysis to improve memory robustness and manufacturability.
Develop reusable memory design methodologies, automation scripts, and design documentation.
Support technology migration and new node development activities.
Participate in design reviews, tape-outs, and post-silicon validation.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline.
5 12 years of experience in SRAM, embedded memory, or memory IP design.
Strong understanding of CMOS transistor-level circuit design and semiconductor memory architecture.
Proven experience in advanced ASIC or SoC development.
Technical Skills Memory Design
SRAM Design
Embedded Memory
Memory Compiler
Memory Macro Design
Bit Cell Design
Memory Architecture
Memory Optimization
Circuit Design
CMOS Circuit Design
Transistor-Level Design
Sense Amplifier Design
Write Driver Design
Row Decoder
Column Decoder
Precharge Circuit
Wordline Driver
I/O Circuit Design
Simulation & Verification
SPICE Simulation
Spectre
HSPICE
Monte Carlo Analysis
Noise Analysis
Timing Analysis
Leakage Analysis
Read Stability
Write Margin
SNM (Static Noise Margin)
Characterization
Memory Characterization
Silicon Validation
PVT Analysis
Reliability Analysis
Yield Analysis
Failure Analysis
EDA Tools
Cadence Virtuoso
Synopsys Custom Compiler
Spectre
HSPICE
Liberate
Calibre
PrimeTime
StarRC
Programming & Automation
Tcl
Python
Perl
Shell Scripting
#LI-SD1
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Location: Bengaluru, India
Work Mode: Onsite
Experience: 5 12 Years
Industry: Semiconductor / VLSI / ASIC Design
Role Overview
We are looking for an experienced SRAM / Memory Design Engineer to develop and optimize embedded memory IP solutions for advanced semiconductor technologies. The role involves SRAM architecture, transistor-level memory circuit design, memory compiler development, read/write optimization, low-power memory design, characterization, and silicon validation for high-performance SoC and ASIC products.
The successful candidate will work closely with Process Technology, Device Engineering, Physical Design, CAD, Product Engineering, and Verification teams to deliver robust, manufacturable memory solutions supporting AI, Automotive, Networking, Data Center, Industrial, and High-Performance Computing applications.
Key Responsibilities
Design and develop high-performance SRAM and embedded memory macros for advanced semiconductor process technologies.
Perform transistor-level memory circuit design, simulation, optimization, and verification.
Optimize read/write margins, stability, leakage power, access time, and memory yield across multiple PVT corners.
Design peripheral circuits including Sense Amplifiers, Write Drivers, Row Decoders, Column Decoders, Precharge Circuits, Wordline Drivers, and I/O circuitry.
Support memory compiler development and memory architecture optimization.
Perform SPICE simulations for functional verification, timing, power, noise, and reliability analysis.
Collaborate with Device, Process Integration, Physical Design, CAD, and Product Engineering teams throughout the design cycle.
Support memory characterization, silicon validation, yield improvement, and customer enablement.
Investigate silicon failures and perform root cause analysis to improve memory robustness and manufacturability.
Develop reusable memory design methodologies, automation scripts, and design documentation.
Support technology migration and new node development activities.
Participate in design reviews, tape-outs, and post-silicon validation.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline.
5 12 years of experience in SRAM, embedded memory, or memory IP design.
Strong understanding of CMOS transistor-level circuit design and semiconductor memory architecture.
Proven experience in advanced ASIC or SoC development.
Technical Skills Memory Design
SRAM Design
Embedded Memory
Memory Compiler
Memory Macro Design
Bit Cell Design
Memory Architecture
Memory Optimization
Circuit Design
CMOS Circuit Design
Transistor-Level Design
Sense Amplifier Design
Write Driver Design
Row Decoder
Column Decoder
Precharge Circuit
Wordline Driver
I/O Circuit Design
Simulation & Verification
SPICE Simulation
Spectre
HSPICE
Monte Carlo Analysis
Noise Analysis
Timing Analysis
Leakage Analysis
Read Stability
Write Margin
SNM (Static Noise Margin)
Characterization
Memory Characterization
Silicon Validation
PVT Analysis
Reliability Analysis
Yield Analysis
Failure Analysis
EDA Tools
Cadence Virtuoso
Synopsys Custom Compiler
Spectre
HSPICE
Liberate
Calibre
PrimeTime
StarRC
Programming & Automation
Tcl
Python
Perl
Shell Scripting
#LI-SD1
Show more Show less