RC
SRAM Development Engineer
Accepting applicationsRapidus Corporation US · Albany, NY
Full-Time Mid_senior AICMOSCadenceCalibreFinFET
Posted
4d ago
Category
Eda
Experience
Mid_senior
Country
United States
Job Title:
SRAM Development Engineer (Roadmap & DTCO) – 2 nm Technology Node and beyond
Team: Enablement / Memory Development
Location: Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)
Overview
Rapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond.
We are seeking talented engineers to join our SRAM Development Team, responsible for SRAM bitcell, peripheral circuit, macro, and compiler development, as well as SRAM technology roadmap planning and DTCO (Device-Technology Co-Optimization).
This role offers the opportunity to work on cutting-edge memory architectures while collaborating closely with process, device, DTCO, and design enablement teams to define scalable SRAM solutions for future technology nodes.
About Rapidus
Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.
Why Join Us
You will play a central leadership role in building the world’s most advanced 2nm and next‑generation enablement ecosystem, shaping the foundation for future semiconductor innovation.
You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)
Key Responsibilities
Design and develop SRAM bitcells, peripheral circuits, SRAM macros, and compilers for advanced technology nodes (2 nm and beyond).
Perform transistor-level circuit design and simulation to meet performance, power, stability, and variability requirements.
Collaborate with process integration and device teams to improve SRAM cell robustness, yield, and manufacturability through DTCO activities.
Define and maintain the SRAM technology roadmap, including scaling strategy, bitcell architecture evolution, and feature planning for future nodes.
Lead and contribute to DTCO studies for SRAM, evaluating device options, layout constructs, Vt choices, and PPA trade-offs.
Work closely with standard cell, GPIO, and logic IP teams to ensure cross-IP alignment and consistent design assumptions.
Participate in SRAM macro architecture definition and compiler feature planning (timing, redundancy, power management).
Conduct layout verification, DRC/LVS debug, parasitic extraction, and variation analysis for SRAM arrays and peripherals.
Analyze silicon test and characterization data and support failure analysis and yield improvement activities.
Work with EDA vendors and PDK teams to define and validate SRAM modeling, sign-off, and enablement flows.
Contribute to SRAM qualification test chips and shuttle programs.
Required Qualifications
B.S. or M.S. in Electrical Engineering, Electronics, or related field.
3+ years of experience in SRAM circuit design, memory architecture, or advanced CMOS memory development.
Strong knowledge of SRAM bitcell design, peripheral circuits, and variability-aware design techniques.
Experience with EDA tools for schematic design, layout, and simulation (e.g., Cadence Virtuoso, Synopsys HSPICE, Siemens Calibre).
Solid understanding of device physics, PVT variation, and reliability challenges at advanced nodes.
Ability to work effectively with cross-functional teams (process, DTCO, EDA, test, and enablement).
Strong communication and technical documentation skills in English.
Preferred Qualifications
Experience with FinFET or nanosheet (GAA) SRAM design.
Experience contributing to SRAM technology roadmap definition or long-term memory scaling strategy.
Familiarity with DTCO methodologies, including device/layout co-optimization and trade-off analysis.
Experience with SRAM compiler development and automation flows.
Hands-on experience with silicon debug, failure analysis, and test-chip bring-up.
Knowledge of EDA PDK development or SRAM model validation flows.
Business-level Japanese proficiency is a plus.
Benefits
Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles)
401k with no employer match
Show more Show less
SRAM Development Engineer (Roadmap & DTCO) – 2 nm Technology Node and beyond
Team: Enablement / Memory Development
Location: Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)
Overview
Rapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond.
We are seeking talented engineers to join our SRAM Development Team, responsible for SRAM bitcell, peripheral circuit, macro, and compiler development, as well as SRAM technology roadmap planning and DTCO (Device-Technology Co-Optimization).
This role offers the opportunity to work on cutting-edge memory architectures while collaborating closely with process, device, DTCO, and design enablement teams to define scalable SRAM solutions for future technology nodes.
About Rapidus
Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.
Why Join Us
You will play a central leadership role in building the world’s most advanced 2nm and next‑generation enablement ecosystem, shaping the foundation for future semiconductor innovation.
You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)
Key Responsibilities
Design and develop SRAM bitcells, peripheral circuits, SRAM macros, and compilers for advanced technology nodes (2 nm and beyond).
Perform transistor-level circuit design and simulation to meet performance, power, stability, and variability requirements.
Collaborate with process integration and device teams to improve SRAM cell robustness, yield, and manufacturability through DTCO activities.
Define and maintain the SRAM technology roadmap, including scaling strategy, bitcell architecture evolution, and feature planning for future nodes.
Lead and contribute to DTCO studies for SRAM, evaluating device options, layout constructs, Vt choices, and PPA trade-offs.
Work closely with standard cell, GPIO, and logic IP teams to ensure cross-IP alignment and consistent design assumptions.
Participate in SRAM macro architecture definition and compiler feature planning (timing, redundancy, power management).
Conduct layout verification, DRC/LVS debug, parasitic extraction, and variation analysis for SRAM arrays and peripherals.
Analyze silicon test and characterization data and support failure analysis and yield improvement activities.
Work with EDA vendors and PDK teams to define and validate SRAM modeling, sign-off, and enablement flows.
Contribute to SRAM qualification test chips and shuttle programs.
Required Qualifications
B.S. or M.S. in Electrical Engineering, Electronics, or related field.
3+ years of experience in SRAM circuit design, memory architecture, or advanced CMOS memory development.
Strong knowledge of SRAM bitcell design, peripheral circuits, and variability-aware design techniques.
Experience with EDA tools for schematic design, layout, and simulation (e.g., Cadence Virtuoso, Synopsys HSPICE, Siemens Calibre).
Solid understanding of device physics, PVT variation, and reliability challenges at advanced nodes.
Ability to work effectively with cross-functional teams (process, DTCO, EDA, test, and enablement).
Strong communication and technical documentation skills in English.
Preferred Qualifications
Experience with FinFET or nanosheet (GAA) SRAM design.
Experience contributing to SRAM technology roadmap definition or long-term memory scaling strategy.
Familiarity with DTCO methodologies, including device/layout co-optimization and trade-off analysis.
Experience with SRAM compiler development and automation flows.
Hands-on experience with silicon debug, failure analysis, and test-chip bring-up.
Knowledge of EDA PDK development or SRAM model validation flows.
Business-level Japanese proficiency is a plus.
Benefits
Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles)
401k with no employer match
Show more Show less