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Sr. Verification Engineer (IRT48ST RM 4301)

Accepting applications

Source-Right · Hyderabad, Telangana, India

Full-Time Senior C++DDREthernetPCIePerl
Estimated market salary
₹49-89 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
1d ago
Category
Verification
Experience
Senior
Country
India
Position: Sr. Verification Engineer (IRT48ST RM 4301)

Job Description

Strong proficiency in SystemVerilog and HDL languages.Hands-on experience with UVM or other industry-standard verification methodologies.
Strong object-oriented programming skills using SystemVerilog and C++.
Ability to write and interpret architectural/design specifications and verification requirements.
Experience in writing verification test plans.
Proficiency in developing complex simulation test benches.
Ability to implement directed and constrained-random test cases.
Experience with functional and code coverage collection, analysis, and closure.
Strong debugging skills for simulation issues, test cases, tools, and DUT (Device Under Test).
Extensive experience in at least one of the high speed protocol related verification (PCIe/Ethernet/DDR/UCIe/CXL/USB).
Proficiency in scripting languages such as Perl, Shell, and Python.
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