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Sr. Staff Engineer, Full-chip Physical Verification and Foundry Sign Off
Accepting applicationsAyar Labs · Bengaluru, Karnataka, India
Full-Time Senior AIASICCadenceCalibreDFT
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Senior
Country
India
Sr. Staff Engineer, Full-Chip Physical Verification and Foundry Sign off
Location: Bangalore (on-site, flexible hours)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we use light instead of electricity to move data faster, farther, and with a fraction of the energy required to fuel the explosive growth of AI models.
Backed by industry leaders including NVIDIA, AMD, and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures.
The Sr. Staff Full-Chip Physical Verification and Foundry Signoff Engineer will own the physical-verification methodology and final database certification for complex mixed-signal SoCs used in high-speed electro-optical engines.
This engineer will be the accountable signoff owner for full-chip DRC, LVS, ERC, PERC, antenna, density, DFM, and related foundry requirements. The role extends beyond running verification tools: it includes methodology development, violation disposition, waiver management, foundry interaction, and authorization of the final GDS/OASIS database for tapeout.
Key Responsibilities
Own full-chip physical-verification methodology, execution, closure, and final tapeout certification.
Drive DRC, LVS, ERC, PERC, antenna, density, DFM, metal-fill, XOR, and connectivity closure.
Develop and maintain hierarchical and incremental PV flows for large mixed-signal SoCs.
Resolve complex LVS issues involving hierarchy, black boxes, analog/custom blocks, multiple power domains, global nets, CDL/SPICE netlists, and parameterized devices.
Own top-level verification of pad rings, bumps, RDL, seal rings, ESD structures, power connectivity, analog interfaces, and custom layout.
Qualify foundry rule decks, runsets, tool versions, PDK updates, and signoff configurations.
Establish processes for violation classification, ownership, review, waiver approval, and foundry disposition.
Coordinate metal-fill generation and post-fill timing, extraction, EMIR, DRC, LVS, and density rechecks.
Maintain auditable signoff checklists, dashboards, release criteria, database checksums, and tapeout-quality gates.
Own final GDS/OASIS stream-out verification and foundry handoff.
Work directly with physical design, analog layout, DFT, package, reliability, foundry, EDA, and external ASIC service teams.
Automate repetitive PV analysis, reporting, triage, and regression activities.
Mentor engineers and establish consistent PV practices across blocks and projects.
Basic Qualifications
BS or MS in Electrical Engineering, Computer Engineering, or a related field.
8+ years of ASIC physical verification or physical design experience.
Demonstrated full-chip PV ownership on at least three successful tapeouts.
Hands-on experience with N3/N3P or comparable leading-edge process nodes.
Mastery of Siemens Calibre nmDRC/nmLVS and experience with Cadence Pegasus or Synopsys ICV.
Deep knowledge of DRC, LVS, ERC, PERC, antenna, density, metal-fill, DFM, and XOR methodologies.
Experience debugging hierarchical, mixed-signal, multi-voltage, and top-level LVS problems.
Strong knowledge of LEF, DEF, GDSII, OASIS, CDL, SPICE, Verilog netlists, and layout connectivity.
Proficiency in Tcl, Python, Perl, shell, or SVRF-based automation.
Experience working directly with foundry rule decks, technical support, and waiver processes.
Preferred Qualifications
Experience with custom analog, high-speed SerDes, photonics-interface, or mixed-signal SoCs.
Experience verifying bump maps, RDL, interposers, 2.5D/3DIC assemblies, and package connectivity.
Experience with ESD, latch-up, reliability, and current-density verification.
Experience developing or qualifying foundry signoff decks and flows.
Experience coordinating tapeouts through external ASIC service providers.
Experience debugging silicon issues traced to layout, connectivity, fill, or physical-verification escapes.
Note To Recruiters
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
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Location: Bangalore (on-site, flexible hours)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we use light instead of electricity to move data faster, farther, and with a fraction of the energy required to fuel the explosive growth of AI models.
Backed by industry leaders including NVIDIA, AMD, and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures.
The Sr. Staff Full-Chip Physical Verification and Foundry Signoff Engineer will own the physical-verification methodology and final database certification for complex mixed-signal SoCs used in high-speed electro-optical engines.
This engineer will be the accountable signoff owner for full-chip DRC, LVS, ERC, PERC, antenna, density, DFM, and related foundry requirements. The role extends beyond running verification tools: it includes methodology development, violation disposition, waiver management, foundry interaction, and authorization of the final GDS/OASIS database for tapeout.
Key Responsibilities
Own full-chip physical-verification methodology, execution, closure, and final tapeout certification.
Drive DRC, LVS, ERC, PERC, antenna, density, DFM, metal-fill, XOR, and connectivity closure.
Develop and maintain hierarchical and incremental PV flows for large mixed-signal SoCs.
Resolve complex LVS issues involving hierarchy, black boxes, analog/custom blocks, multiple power domains, global nets, CDL/SPICE netlists, and parameterized devices.
Own top-level verification of pad rings, bumps, RDL, seal rings, ESD structures, power connectivity, analog interfaces, and custom layout.
Qualify foundry rule decks, runsets, tool versions, PDK updates, and signoff configurations.
Establish processes for violation classification, ownership, review, waiver approval, and foundry disposition.
Coordinate metal-fill generation and post-fill timing, extraction, EMIR, DRC, LVS, and density rechecks.
Maintain auditable signoff checklists, dashboards, release criteria, database checksums, and tapeout-quality gates.
Own final GDS/OASIS stream-out verification and foundry handoff.
Work directly with physical design, analog layout, DFT, package, reliability, foundry, EDA, and external ASIC service teams.
Automate repetitive PV analysis, reporting, triage, and regression activities.
Mentor engineers and establish consistent PV practices across blocks and projects.
Basic Qualifications
BS or MS in Electrical Engineering, Computer Engineering, or a related field.
8+ years of ASIC physical verification or physical design experience.
Demonstrated full-chip PV ownership on at least three successful tapeouts.
Hands-on experience with N3/N3P or comparable leading-edge process nodes.
Mastery of Siemens Calibre nmDRC/nmLVS and experience with Cadence Pegasus or Synopsys ICV.
Deep knowledge of DRC, LVS, ERC, PERC, antenna, density, metal-fill, DFM, and XOR methodologies.
Experience debugging hierarchical, mixed-signal, multi-voltage, and top-level LVS problems.
Strong knowledge of LEF, DEF, GDSII, OASIS, CDL, SPICE, Verilog netlists, and layout connectivity.
Proficiency in Tcl, Python, Perl, shell, or SVRF-based automation.
Experience working directly with foundry rule decks, technical support, and waiver processes.
Preferred Qualifications
Experience with custom analog, high-speed SerDes, photonics-interface, or mixed-signal SoCs.
Experience verifying bump maps, RDL, interposers, 2.5D/3DIC assemblies, and package connectivity.
Experience with ESD, latch-up, reliability, and current-density verification.
Experience developing or qualifying foundry signoff decks and flows.
Experience coordinating tapeouts through external ASIC service providers.
Experience debugging silicon issues traced to layout, connectivity, fill, or physical-verification escapes.
Note To Recruiters
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Show more Show less