Sr. Staff Engineer, EMIR/Power Integrity

Sr. Staff Engineer, EMIR / Power Integrity

Location: Bengaluru (on-site, flexible hours)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we use light instead of electricity to move data faster, farther, and with a fraction of the energy required to fuel the explosive growth of AI models.

Backed by industry leaders including NVIDIA, AMD, and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures.

The Sr. Staff Engineer, EMIR / Power Integrity will own full-chip power-integrity analysis, closure, and signoff for advanced-node SoCs integrating high-speed digital, analog/mixed-signal, and photonics-interface components.

This is a hands-on technical-lead role spanning early architecture and floorplanning through final tapeout. The successful candidate will not simply run EMIR tools; they will interpret results, identify risks, define corrective actions, and drive cross-functional closure across physical design, circuit design, package, and signoff teams.

Key Responsibilities

Own full-chip static and dynamic IR-drop, electromigration, and power-integrity analysis from early floorplanning through final tapeout.
Define EMIR signoff methodology, scenario coverage, guardbands, acceptance criteria, waiver processes, and tapeout-quality gates.
Develop and optimize full-chip power-delivery strategies, including power-domain planning, power-grid architecture, bump assignment, macro power connections, via structures, and decap allocation.
Perform vectorless and vector-based dynamic voltage-drop analysis using realistic VCD, FSDB, SAIF, and workload-derived activity.
Analyze functional, calibration, power-up, scan-shift, scan-capture, BIST, and other high-current operating modes.
Incorporate package, interposer, bump, and RDL parasitic models into chip-level power-integrity analysis.
Sign off power and ground grids, critical current paths, vias, bumps, power switches, memories, and high-current analog/mixed-signal interfaces.
Identify EMIR risks early and drive corrective actions with block physical-design, full-chip integration, analog/mixed-signal, package, circuit-design, and reliability teams.
Recommend and evaluate fixes involving floorplan, power-grid topology, bump allocation, decap insertion, routing, via reinforcement, placement, clocking, and circuit activity.
Correlate architectural estimates, implementation-stage results, extracted post-layout data, package models, and final signoff results.
Establish measurable rail-level voltage-drop, current-density, and reliability budgets.
Develop dashboards that clearly communicate convergence, remaining violations, risk levels, ownership, and tapeout readiness.
Build scalable hierarchical EMIR methodologies, automation, regression flows, and review checkpoints across multiple projects.
Qualify analysis models, foundry technology files, tool versions, extraction settings, and signoff configurations.
Work directly with foundries, EDA vendors, package partners, and external ASIC service providers to resolve technical issues.
Mentor physical-design engineers and establish repeatable power-integrity practices across the organization.

Basic Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or a related field.
8+ years of experience in ASIC physical design, power integrity, or EMIR analysis.
Proven ownership of full-chip EMIR closure and signoff on successful advanced-node SoC tapeouts.
Strong hands-on experience with Ansys RedHawk-SC, Cadence Voltus, or equivalent industry-standard power-integrity tools.
Experience with advanced FinFET process technologies; hands-on N5 or N3-class experience is strongly preferred.
Deep understanding of power-distribution networks, static and dynamic voltage drop, electromigration, current-density limits, decap strategy, power gating, and package interactions.
Experience developing realistic current and activity models for vectorless and vector-based analysis.
Experience analyzing complex SoCs containing high-speed digital, custom analog/mixed-signal, memory, and clocking components.
Strong knowledge of physical-design implementation, including floorplanning, power planning, placement, clocking, routing, and signoff extraction.
Experience with extraction and power-analysis tools such as StarRC, Quantus, PrimePower, Joules, or equivalent.
Working knowledge of multi-voltage designs, UPF, power switches, always-on domains, and low-power implementation.
Proficiency in Tcl, Python, Perl, shell, or other scripting and automation languages.
Demonstrated ability to communicate technical risks clearly and drive closure across teams without relying on direct reporting authority.

Preferred Qualifications

Experience with TSMC N3/N3P technology and associated EMIR signoff requirements.
Experience with co-packaged optics, silicon photonics, high-speed SerDes, UCIe, HBM, or other high-bandwidth interfaces.
Experience with 2.5D/3DIC systems, chiplets, interposers, RDL, and package-aware power-integrity analysis.
Experience with package-model generation, chip-package power-delivery co-design, and bump-current optimization.
Understanding of electrothermal analysis, self-heating, aging, reliability, and temperature-dependent electromigration.
Experience correlating pre-layout estimates, implementation analysis, signoff results, and post-silicon measurements.
Experience debugging silicon power-integrity, voltage-droop, or reliability issues.
Experience working directly with leading-edge foundries, OSATs, EDA vendors, and external ASIC service providers.

Note To Recruiters

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
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