Sr. SRAM Layout Design Engineer with Tsmc 3nm or lower

What you will be doing:


· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies
.· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly
.· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows
.· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout
.· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained
.· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues
.· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery
.· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints
.· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team

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What we need to se
e:· Have a BSEE or equivalent experien
ce· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layou
t.· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimension
s.· Solid grasp of SRAM and memory layout principle
s.· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessmen
t.· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tool
s.· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verificatio
n.· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertis
e.· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry team
s.· Clear communication, strong ownership, good judgment, and the ability to mentor other engineer
s.· Knowledge of layout automation or AI tools is a definite plu

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