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Sr. SRAM Layout Design Engineer
Accepting applicationsProgrammers.io · Santa Clara, CA
Full-Time Mid_senior AICMOSCadenceCalibreFinFET
Posted
19h ago
Category
Eda
Experience
Mid_senior
Country
United States
Position: Sr. SRAM Layout Design Engineer
Location: Santa Clara, CA (Onsite)
Hire Type: Full Time
Experience: 10+ Years
What you will be doing:
· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
What we need to see:
· Have a BSEE or equivalent experience
· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
· Solid grasp of SRAM and memory layout principles.
· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
· Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
· Knowledge of layout automation or AI tools is a definite plus.
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Location: Santa Clara, CA (Onsite)
Hire Type: Full Time
Experience: 10+ Years
What you will be doing:
· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
What we need to see:
· Have a BSEE or equivalent experience
· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
· Solid grasp of SRAM and memory layout principles.
· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
· Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
· Knowledge of layout automation or AI tools is a definite plus.
Show more Show less