MG
Sr Principal Engineer, Design Technologist
Accepting applicationsMetric Geo · Dallas, TX
Full-Time Mid_senior CadenceRTLSoCSynopsys
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Metric Search are exclusively partnering with a world-renowned semiconductor organization ($5B+ revenue per annum), who are seeking to hire a Sr. Principal Engineer to lead their Physical Design Technology Team, shaping how the next generation of SoCs get designed and built.
They are seeking someone to translate process technology capabilities into design guidelines and methodology improvements that deliver best in class PPA, DFM, and yield across advanced process nodes.
This is a great opportunity to join a leading organisation with the chance to define next generation design methodology, shape the company's EDA strategy, and act as the technical glue between process, design, and product functions.
Responsible for:
Own technology benchmarking efforts and build standardized metrics for comparing node options against each other
Sit alongside architecture, RTL, and physical design teams to keep design decisions grounded in process reality
Set the design methodology and sign off strategy for advanced nodes, balancing performance targets against manufacturability
Push forward EDA flow improvements across synthesis, place & route, timing, power, and verification
Requirements:
15+ years in SoC design, physical design, EDA methodology, or process integration, including senior technical roles
Strong grasp of advanced-node fabrication, PDK development, and how process and design interact
Practical experience navigating timing, power, and signal integrity challenges on modern chips
Comfortable working with major EDA toolsets (Cadence, Synopsys, Siemens, or similar)
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They are seeking someone to translate process technology capabilities into design guidelines and methodology improvements that deliver best in class PPA, DFM, and yield across advanced process nodes.
This is a great opportunity to join a leading organisation with the chance to define next generation design methodology, shape the company's EDA strategy, and act as the technical glue between process, design, and product functions.
Responsible for:
Own technology benchmarking efforts and build standardized metrics for comparing node options against each other
Sit alongside architecture, RTL, and physical design teams to keep design decisions grounded in process reality
Set the design methodology and sign off strategy for advanced nodes, balancing performance targets against manufacturability
Push forward EDA flow improvements across synthesis, place & route, timing, power, and verification
Requirements:
15+ years in SoC design, physical design, EDA methodology, or process integration, including senior technical roles
Strong grasp of advanced-node fabrication, PDK development, and how process and design interact
Practical experience navigating timing, power, and signal integrity challenges on modern chips
Comfortable working with major EDA toolsets (Cadence, Synopsys, Siemens, or similar)
Show more Show less