NS
Sr.Principal Digital IP Engineer
Accepting applicationsNXP Semiconductors · Bengaluru, Karnataka, India
Full-Time Mid_senior RTLSoCSystemVerilogVHDLVerilog
Estimated market salary
₹18-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description
In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.
Key responsibilitie
Work with architecture teams and put up the micro-architecture based on the IP requirement
Develop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specification
Optimize designs for power, performance, and are
Perform design checks such as Lint, CDC, synthesis, and ST
ADrive bug fixing and closur
Support design reviews and sign-off processe
Collaborate with verification teams on test plans and coverage closur
Required skil
lsStrong experience in RTL design (Verilog/SystemVerilog/VHD
L)Solid understanding of SoC/IP design and integrati
onHands-on experience with:Lint, CDC, synthesis, timing analys
isExperience in Low-power design techniqu
Preferred ski
llsExperience in full-cycle IP/SoC developm
entExposure to formal verification or low-power fl
owsExperience with post-silicon validation and bring
Show more Show less
In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.
Key responsibilitie
Work with architecture teams and put up the micro-architecture based on the IP requirement
Develop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specification
Optimize designs for power, performance, and are
Perform design checks such as Lint, CDC, synthesis, and ST
ADrive bug fixing and closur
Support design reviews and sign-off processe
Collaborate with verification teams on test plans and coverage closur
Required skil
lsStrong experience in RTL design (Verilog/SystemVerilog/VHD
L)Solid understanding of SoC/IP design and integrati
onHands-on experience with:Lint, CDC, synthesis, timing analys
isExperience in Low-power design techniqu
Preferred ski
llsExperience in full-cycle IP/SoC developm
entExposure to formal verification or low-power fl
owsExperience with post-silicon validation and bring
Show more Show less
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