CS
Sr Principal DFT Design Engineer
Accepting applicationsCadence System Design and Analysis · Greater Bengaluru Area
Full-Time Mid_senior ATPGBoundary scanDFTRTL
Estimated market salary
₹72-129 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
14 Jun
Category
Test
Experience
Mid_senior
Country
India
Experience: 12- 16 years
Location - Bangalore/Pune
Responsibilities:
· Complete DFT ownership of projects including:
Test architecture definition.
Identifying and implementing RTL changes for DFT.
Performing scan insertion, LEC checks, low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Experience working on very high speed and low power designs.
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Location - Bangalore/Pune
Responsibilities:
· Complete DFT ownership of projects including:
Test architecture definition.
Identifying and implementing RTL changes for DFT.
Performing scan insertion, LEC checks, low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Experience working on very high speed and low power designs.
Show more Show less