VT
Sr. Mixed Signal Design Engineer
Accepting applicationsVeriFast Technologies · San Jose, CA
Contract Mid_senior AnalogCADENCEMixed SignalSPICEVerilog
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Title: Principal, Design Engineer, Pathfinding
Locations: Folsom, CA, Boise, ID, San Jose, CA (onsite Only)
Type: Contract
Rate: $80 - $150 per hour
The leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.
As a Design Engineer in the Pathfinding Design Team, you will play a key role in shaping next-generation memory technologies. This position involves contributing to array architecture definition and analysis, as well as leading the design of analog, basic digital, and mixed-signal circuits for advanced memory technologies, including DRAM and Emerging memories. You will work on novel concept development, circuit simulation, optimization, and floor planning to enable groundbreaking memory solutions!
Responsibilities
Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
Performing circuit modeling, sensitivity analyses, and assisting in developing validation through widely recognized simulation software and tools
Designing on-silicon test chips and leading required tape-out revisions
Coordinating and collaborating with the layout team, including floor-planning, placement, and routing
Performing verification processes with modeling and simulation using industry-standard simulators
Qualifications
Demonstrated experience in mix-signal, digital, or analog IC design and development for volatile or nonvolatile memory technology
Proven experience in IC design with exposure to Regulator, Charge Pump, Oscillator, Current reference, Bandgap, and Comparator design experience is required
Exposure to modeling and simulation of ICs using SPICE and Verilog
10+ years of demonstrated ability in communicating with technical and non-technical team members across a large organization
BSEE or MSEE in Electrical Engineering with a minimum of 10 years of relevant Semiconductor Manufacturing experience
cePreferred Qualificatio
MSEE + 10 years’ post-graduate mix-signal or analog IC design experience
10+ years of exposure to circuit debugging in collaboration with other engineering team
Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extractions)
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Locations: Folsom, CA, Boise, ID, San Jose, CA (onsite Only)
Type: Contract
Rate: $80 - $150 per hour
The leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.
As a Design Engineer in the Pathfinding Design Team, you will play a key role in shaping next-generation memory technologies. This position involves contributing to array architecture definition and analysis, as well as leading the design of analog, basic digital, and mixed-signal circuits for advanced memory technologies, including DRAM and Emerging memories. You will work on novel concept development, circuit simulation, optimization, and floor planning to enable groundbreaking memory solutions!
Responsibilities
Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
Performing circuit modeling, sensitivity analyses, and assisting in developing validation through widely recognized simulation software and tools
Designing on-silicon test chips and leading required tape-out revisions
Coordinating and collaborating with the layout team, including floor-planning, placement, and routing
Performing verification processes with modeling and simulation using industry-standard simulators
Qualifications
Demonstrated experience in mix-signal, digital, or analog IC design and development for volatile or nonvolatile memory technology
Proven experience in IC design with exposure to Regulator, Charge Pump, Oscillator, Current reference, Bandgap, and Comparator design experience is required
Exposure to modeling and simulation of ICs using SPICE and Verilog
10+ years of demonstrated ability in communicating with technical and non-technical team members across a large organization
BSEE or MSEE in Electrical Engineering with a minimum of 10 years of relevant Semiconductor Manufacturing experience
cePreferred Qualificatio
MSEE + 10 years’ post-graduate mix-signal or analog IC design experience
10+ years of exposure to circuit debugging in collaboration with other engineering team
Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extractions)
Show more Show less
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