C
Sr. Manager, ASIC Design
Accepting applicationsCredo · San Jose, CA
Full-Time Principal AIASICDFTEthernetMentor
Posted
11 Jun
Category
Design
Experience
Principal
Country
United States
About the role
As a Sr. Manager, ASIC Design, you will lead a team of engineers in delivering complex ASIC designs from specification to tape-out. This role covers all aspects of front-end ASIC design, including microarchitecture, RTL implementation, and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and partner with system teams for chip bring-up and validation.
Base salary range is $200,000 to $230,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Why Credo
Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.
Qualifications
Basic Qualifications
MS degree in EE/CS with 10+ years of relevant experience.
Deep understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficient in Verilog/SystemVerilog RTL design.
Knowledge of synthesis and static timing analysis.
Experience developing testbenches and test cases; familiarity with UVM.
Experience with gate-level simulations, chip bring-up, and validation.
Proven track record of successful production tape-outs.
Hands-on experience with STA and timing closure.
Familiarity with DFT methodology and physical design flow.
Experience in high-speed Serdes design.
Preferred Qualifications
Expertise in scripting languages (Python, Tcl, Perl, Shell).
Strong planning and estimation skills.
Excellent communication and leadership abilities.
Familiar with Ethernet (802.3) standards.
Responsibilities
Lead a team of engineers to deliver chips from specification through tapeout.
Mentor junior engineers on design methodologies, verification flows, and best practices.
Develop and maintain detailed microarchitecture and design specifications.
Design, implement, and debug complex logic blocks.
Integrate and validate IPs from internal and external vendors.
Support front-end integration activities, including Lint, CDC, synthesis, and ECO processes.
Create functional tests and testbenches; perform RTL and gate-level verification and simulations.
Collaborate with verification, DFT, and physical design teams to ensure successful tapeout.
Bring up, validate, and debug functional features on silicon.
Work closely with software, firmware, applications, and systems teams to deliver a high-quality product.
About Credo
Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.
Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.
Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.
Show more Show less
As a Sr. Manager, ASIC Design, you will lead a team of engineers in delivering complex ASIC designs from specification to tape-out. This role covers all aspects of front-end ASIC design, including microarchitecture, RTL implementation, and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and partner with system teams for chip bring-up and validation.
Base salary range is $200,000 to $230,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Why Credo
Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.
Qualifications
Basic Qualifications
MS degree in EE/CS with 10+ years of relevant experience.
Deep understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficient in Verilog/SystemVerilog RTL design.
Knowledge of synthesis and static timing analysis.
Experience developing testbenches and test cases; familiarity with UVM.
Experience with gate-level simulations, chip bring-up, and validation.
Proven track record of successful production tape-outs.
Hands-on experience with STA and timing closure.
Familiarity with DFT methodology and physical design flow.
Experience in high-speed Serdes design.
Preferred Qualifications
Expertise in scripting languages (Python, Tcl, Perl, Shell).
Strong planning and estimation skills.
Excellent communication and leadership abilities.
Familiar with Ethernet (802.3) standards.
Responsibilities
Lead a team of engineers to deliver chips from specification through tapeout.
Mentor junior engineers on design methodologies, verification flows, and best practices.
Develop and maintain detailed microarchitecture and design specifications.
Design, implement, and debug complex logic blocks.
Integrate and validate IPs from internal and external vendors.
Support front-end integration activities, including Lint, CDC, synthesis, and ECO processes.
Create functional tests and testbenches; perform RTL and gate-level verification and simulations.
Collaborate with verification, DFT, and physical design teams to ensure successful tapeout.
Bring up, validate, and debug functional features on silicon.
Work closely with software, firmware, applications, and systems teams to deliver a high-quality product.
About Credo
Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.
Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.
Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.
Show more Show less
Similar Jobs
M
MTS, Analog Design Engineering
Micron · Boise, United States, North America
M
Senior Engineer, STPG PE (FDV-Verilog)
Micron · Singapore, Singapore, Asia
M
Digital IC Design Engineer - Early Career
Marvell · Westborough, United States, North America
M
Staff Firmware/Software Engineer- Embedded SoC/Microcontroller/DSP/SERDES/AEC/Microled/ODSP/PHY/AI Connectivity
Marvell · Santa Clara, United States, North America