S
Sr. Layout Design Engineer
Accepting applicationsSiTime · Bengaluru, Karnataka, India
Full-Time Senior MEMSCadenceLayoutTiming
Estimated market salary
₹59-106 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Senior
Country
India
About SiTime
SiTime is the Precision Timing company.
Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .
Job Summary
The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality
Responsibilities
Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
Perform schematic-driven layout and design constraints
Design die-area efficient layouts according to circuit designer requirements
Perform block or top-level layout designs
Perform floor-planning, power line planning, shielding, and device-matching layout
Verify layouts. Pass DRC, LVS, and ERC
Contribute to various chip-level routing and layout needs
Perform chip level integration, verifications, and tape-out
Support other projects as needed by management
Train junior layout engineers and offshore layout contractors
Contribute to developing common best practices and workflow across all sites
Contribute to build process and procedures to achieve high layout quality
Qualifications & Requirements
BA/BS Degree in Layout Design or related field or equivalent experience
10 years’ experience with layout design for analog and full-custom digital blocks
Experience TSMC 180nm, 65nm, 22nm process technologies
Proficient in using layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
Experience in chip‐level floor planning and analog block integration
Experience chip level integration, verifications, and tape-out
Ability to use productivity‐enhancing tools and design scripts to further automate tasks is also desirable
Must be able to lift, push, and pull up to 5 lbs
Desired Characteristics & Attributes
Attention to detail, organized, accurate and can produce efficient layout techniques
Has a good track record of on time work delivery
Has a self-motivated, team player with good communication skills
Ability to work well with others in a fast-paced collaborative team environment
Compensation Range
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.
In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.
Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.
Innovation on Top – Philosophies of Innovation with Rajesh Vashist
Fabrication Knowledge – An Interview with Rajesh Vashist
SiTime Corporation – YouTube
Show more Show less
SiTime is the Precision Timing company.
Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .
Job Summary
The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality
Responsibilities
Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
Perform schematic-driven layout and design constraints
Design die-area efficient layouts according to circuit designer requirements
Perform block or top-level layout designs
Perform floor-planning, power line planning, shielding, and device-matching layout
Verify layouts. Pass DRC, LVS, and ERC
Contribute to various chip-level routing and layout needs
Perform chip level integration, verifications, and tape-out
Support other projects as needed by management
Train junior layout engineers and offshore layout contractors
Contribute to developing common best practices and workflow across all sites
Contribute to build process and procedures to achieve high layout quality
Qualifications & Requirements
BA/BS Degree in Layout Design or related field or equivalent experience
10 years’ experience with layout design for analog and full-custom digital blocks
Experience TSMC 180nm, 65nm, 22nm process technologies
Proficient in using layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
Experience in chip‐level floor planning and analog block integration
Experience chip level integration, verifications, and tape-out
Ability to use productivity‐enhancing tools and design scripts to further automate tasks is also desirable
Must be able to lift, push, and pull up to 5 lbs
Desired Characteristics & Attributes
Attention to detail, organized, accurate and can produce efficient layout techniques
Has a good track record of on time work delivery
Has a self-motivated, team player with good communication skills
Ability to work well with others in a fast-paced collaborative team environment
Compensation Range
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.
In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.
Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.
Innovation on Top – Philosophies of Innovation with Rajesh Vashist
Fabrication Knowledge – An Interview with Rajesh Vashist
SiTime Corporation – YouTube
Show more Show less