S
SR DFT Engineer
Accepting applicationsSivaltech · San Francisco Bay Area
Full-Time Mid_senior ATPGBISTDFTJTAGMentor
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
United States
🚨 Sivaltech Hiring | Senior DFT Engineer/ Lead 🚨
📍 Bay Area, CA | Full-Time
Sivaltech is hiring an experienced Senior DFT Architect / Lead for advanced multi-chip SoC programs in 7nm and below technologies.
Skills Required
Scan, ATPG, MBIST, Memory Repair, OCC, LBIST
BSD (ACJTAG/DCJTAG)
Mentor/Synopsys DFT tools
SDC constraints, RTL & GLS simulation
SerDes experience
Verilog/SystemVerilog, TCL/Perl/Python
Multiple tape-outs in 7nm or below
Experience
✔ 15+ years in DFT/SoC design
✔ Bachelor’s/Master’s in EE or related field
📩 Interested candidates can share resumes to sridevi@sivaltech.com
Show more Show less
📍 Bay Area, CA | Full-Time
Sivaltech is hiring an experienced Senior DFT Architect / Lead for advanced multi-chip SoC programs in 7nm and below technologies.
Skills Required
Scan, ATPG, MBIST, Memory Repair, OCC, LBIST
BSD (ACJTAG/DCJTAG)
Mentor/Synopsys DFT tools
SDC constraints, RTL & GLS simulation
SerDes experience
Verilog/SystemVerilog, TCL/Perl/Python
Multiple tape-outs in 7nm or below
Experience
✔ 15+ years in DFT/SoC design
✔ Bachelor’s/Master’s in EE or related field
📩 Interested candidates can share resumes to sridevi@sivaltech.com
Show more Show less
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