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Sr DFT Engineer
Accepting applicationsMythic · Bengaluru, Karnataka, India
Full-Time Mid_senior AIATEATPGAnalogBIST
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
India
About us:
Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India).
About This Role:
Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is implementaiton of DFT features on Mythic's chips.
You will be the working on all aspects of DFT for sub-system-level blocks which form the SoC. You will need to contribute, and ideally, have ownership of all the aspects of DFT such as MBIST, IJTAG, Scan and ATPG . You will contribute to the methodology development to establish flow for all DFT features and enable first-pass success of these chips. You are expected to be involved and contribute to every phase of the design cycle from Concept to Silicon.
Beyond DFT for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the RTL design , Physical design, STA and analog design teams at Mythic.
Must Have
BS/MS/PhD in EE/ECE
At least 4+ years of industry experience
Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST)
Experience with SoC Level DFT Integration, Verification and RTL design for DFT
Experience with DFT strategies like Scan insertion, TPI, SSN, Hierarchical DFT and ATPG
Pre-Silicon test planning & verification strategy
Knowledge & experience of low power concepts, clock gating, power gating is a plus
Adept at root cause analysis and resolving DFT implementation issues
Must have good communication skills and the ability to work in a worldwide team environment
Good To Have
A past experience of working on an AI processor design is a huge plus
Experience working at startups
Knowledge of Low power DFT solutions
Experience of working with STA team to define DFT timing constraints
Working with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvement
Proficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilog
Good script skills including Perl, Tcl, Python, etc.
Knowledge of chiplet-based design limitations and their impact on physical design.
Experience in Sub-10nm designs
Show more Show less
Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India).
About This Role:
Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is implementaiton of DFT features on Mythic's chips.
You will be the working on all aspects of DFT for sub-system-level blocks which form the SoC. You will need to contribute, and ideally, have ownership of all the aspects of DFT such as MBIST, IJTAG, Scan and ATPG . You will contribute to the methodology development to establish flow for all DFT features and enable first-pass success of these chips. You are expected to be involved and contribute to every phase of the design cycle from Concept to Silicon.
Beyond DFT for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the RTL design , Physical design, STA and analog design teams at Mythic.
Must Have
BS/MS/PhD in EE/ECE
At least 4+ years of industry experience
Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST)
Experience with SoC Level DFT Integration, Verification and RTL design for DFT
Experience with DFT strategies like Scan insertion, TPI, SSN, Hierarchical DFT and ATPG
Pre-Silicon test planning & verification strategy
Knowledge & experience of low power concepts, clock gating, power gating is a plus
Adept at root cause analysis and resolving DFT implementation issues
Must have good communication skills and the ability to work in a worldwide team environment
Good To Have
A past experience of working on an AI processor design is a huge plus
Experience working at startups
Knowledge of Low power DFT solutions
Experience of working with STA team to define DFT timing constraints
Working with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvement
Proficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilog
Good script skills including Perl, Tcl, Python, etc.
Knowledge of chiplet-based design limitations and their impact on physical design.
Experience in Sub-10nm designs
Show more Show less