II
Sr. Design Verification Engineer
Accepting applicationsInterSources Inc · San Jose, CA
Full-Time Mid_senior EthernetPCIeRTLUVMVerilog
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study and 9+ years of industry experience.
9+ years of experience developing verification collateral in Verilog, System Verilog and UVM.
7+ years with Ethernet/PCIe/CXL protocol verification is required.
7+ years in UVM Fluency is a must.
7+ years of complex coverage driven random constraint UVM environments.
7+ years of experience with High level Specification into test plan and developing tests cases.
7+ years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.
Good communication skills.
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9+ years of experience developing verification collateral in Verilog, System Verilog and UVM.
7+ years with Ethernet/PCIe/CXL protocol verification is required.
7+ years in UVM Fluency is a must.
7+ years of complex coverage driven random constraint UVM environments.
7+ years of experience with High level Specification into test plan and developing tests cases.
7+ years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.
Good communication skills.
Show more Show less