Sr. Design Engineer 2

Key Responsibilities

Develop micro-architecture specifications based on system requirements.
Design and implement RTL using Verilog/SystemVerilog.
Perform RTL coding, linting, CDC checks, and synthesis.
Work closely with verification teams for testbench support and debug.
Participate in design reviews and provide technical solutions.
Perform block-level and SoC-level integration.
Support STA, DFT, and physical design teams during implementation.
Analyze and debug functional and timing issues.
Ensure design meets power, performance, and area (PPA) targets.
Collaborate with cross-functional teams including firmware and validation.

Required Skills & Qualifications

5–8 years of hands-on experience in RTL design for ASIC/SoC.
Strong expertise in Verilog/SystemVerilog.
Experience in micro-architecture and high-speed digital design.
Good understanding of synthesis, STA, CDC, and low-power design concepts.
Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor).
Strong debugging and problem-solving skills.
Knowledge of scripting languages (Perl/Python/TCL) is a plus.
Familiarity with AMBA protocols (AXI/AHB/APB) preferred.
Experience in IP integration and SoC architecture.

Preferred Qualifications

Experience in high-speed interfaces (PCIe, USB, Ethernet, DDR, etc.).
Exposure to low-power design techniques (UPF/CPF).
Experience in 7nm/5nm or advanced technology nodes is an advantage.
Knowledge of FPGA prototyping is a plus.

Education

B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI / related field.
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