Sr Design and verification engineer

Freshers do not apply

Qualifications
Should have 5-10 years of RTL Verification experience, preferably using SystemVerilog and UVM

Role & responsibilities
RTL Verification experience, preferably using SystemVerilog and UVM
Understanding of computer architecture, including processor microarchitecture, bus protocols, and memory systems
Expertise in Functional Verification techniques, including developing test plans, testbench development, and functional coverage analysis
Strong debugging skills, including experience with industry-standard debuggers and waveform viewers
Excellent written and verbal communication skills, as well as the ability to work collaboratively in a team environment
Bachelor's or Master's degree in Electrical or Computer Engineering or a related field
Experience with scripting languages such as Perl or Python is a plus
Familiarity with industry-standard simulators, such as Cadence Incisive and Synopsys VCS is a plus




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