Sr. ASIC/SoC DFT Engineer

This role is fully remote.

Please submit your resume and send to recruiters@vsearchgroup.com if you are interested. Thank you!

Job Summary
We are seeking a Sr. ASIC/SoC DFT Engineer with strong hands-on experience implementing and verifying DFT solutions for complex digital and mixed-signal SoCs, with particular expertise in Siemens Tessent.

Responsibilities
Define and implement DFT architecture for hierarchical digital SoCs.
Perform DFT insertion including Scan Compression, Boundary Scan, MBIST, and LBIST.
Verify inserted DFT logic at both block and top-chip levels.
Generate ATPG patterns and perform test coverage analysis for Stuck-at, Transition, Path Delay, and at-speed faults.
Perform fault simulation and identify opportunities to improve overall test coverage.
Generate test patterns for ATE and support functional/custom test pattern development.
Collaborate with design and test engineering teams on DFT implementation and silicon bring-up.
Support post-silicon ATE test program bring-up, troubleshooting, and test-time optimization.

Qualifications
5+ years of industry experience implementing and verifying DFT/DFD techniques for digital or mixed-signal designs.
Strong experience with hierarchical SoC DFT implementation.
Strong knowledge of Scan, Scan Compression, ATPG, JTAG, Boundary Scan, MBIST, LBIST, and fault simulation.
Strong hands-on experience with Siemens Tessent tools and DFT flows required.
Familiarity with Cadence Xcelium, Genus, and Tempus preferred.
Familiarity with SystemVerilog.
Experience with ATE pattern generation and test coverage analysis.
Degree in Electrical Engineering, Computer Engineering, or a related field.
Strong written and verbal English communication skills.
Show more Show less