SoC Verification Engineer | UVM & System Verilog Specialist

Responsibilities:

Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:

Active involvement with architecture team during the spec definition phase
Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics
SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs
Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities
Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines

Qualifications:

• 3- 5 of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations


Skills:


Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc.
Strong in digital design fundamentals, computer organization & architectures and bus protocols
Excellent debugging skills with Verilog/VHDL designs
Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc
Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus
Good problem-solving skills
Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows
Exposure to CDC DV, Post silicon verification and functional safety is an added advantage
Effective communication skills to interact seamlessly with all stakeholders
Must be highly focused and remain committed to obtaining closure on project goals
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