SOC Power Thermal Performance / PNP

Role Summary
Lead the architecture and delivery of end-to-end SoC power, performance, and thermal limit management solutions. This role drives cohesive HW–FW–SW co-design to protect silicon health while maximizing sustained performance across workloads, process corners, and form factors.
Key Responsibilities
Define system-level power, thermal, voltage, and current limits, integrating hardware triggers, firmware policies, and software mitigations.
Architect real-time telemetry and sensing (Voltage, Current, Temperature, Aging) to monitor silicon behavior and enable fast, reliable mitigations.
Standardize Power Telemetry, Estimators, Droop Detectors, and Thermal monitors across IPs and platforms.
Drive evolution of power and thermal sensing IPs and trigger mechanisms for rising current density and thermal constraints.
Define performance-impact profiles for power and thermal mitigations (throttling, DVFS, clock modulation, workload shaping).
Lead post-silicon validation, correlating physical silicon behavior with architectural intent.
Build cross-functional consensus (HW, FW, OS, Power SW) and drive ROI-based roadmap decisions.
Qualifications
BS in EE/CE/CS (MS/PhD preferred).
7+ years in SoC power, performance, and thermal management or low-power architecture.
Experience from architecture through post-silicon productization.
Expertise in areas such as peak power, PDN droop, thermal management, adaptive DVFS, and reliability monitors.
Strong cross-functional leadership and technical influence.

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