N
SoC Physical Design Engineer
Accepting applicationsNokia · San Jose, CA
Full-Time Mid_senior ASICCalibreInnovusPerlRTL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Description
You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics.
NION2026
Italy salary range: 29,302.33 - 64,054.55 EUR
How You Will Contribute And What You Will Learn
Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
Perform technical evaluations of IP vendors, process nodes and provide recommendations
Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
Perform Physical verification and IR/EM analysis on blocks as well as top
Key Skills And Experience
3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk
Scripting experience in TCL, python or Perl
Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
About The Team
Some of our benefits:
Flexible and hybrid working schemes
A minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)
Life insurance to all employees to provide peace of mind and financial security
Well-being programs to support your mental and physical health
Opportunities to join and receive support from Nokia Employee Resource Groups (NERGs)
Employee Growth Solutions to support your personalized career & skills development
Diverse pool of Coaches & Mentors to whom you have easy access
A learning environment which promotes personal growth and professional development - for your role and beyond
Show more Show less
You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics.
NION2026
Italy salary range: 29,302.33 - 64,054.55 EUR
How You Will Contribute And What You Will Learn
Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
Perform technical evaluations of IP vendors, process nodes and provide recommendations
Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
Perform Physical verification and IR/EM analysis on blocks as well as top
Key Skills And Experience
3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk
Scripting experience in TCL, python or Perl
Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
About The Team
Some of our benefits:
Flexible and hybrid working schemes
A minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)
Life insurance to all employees to provide peace of mind and financial security
Well-being programs to support your mental and physical health
Opportunities to join and receive support from Nokia Employee Resource Groups (NERGs)
Employee Growth Solutions to support your personalized career & skills development
Diverse pool of Coaches & Mentors to whom you have easy access
A learning environment which promotes personal growth and professional development - for your role and beyond
Show more Show less