C
SOC Performance Verification Engineer
Accepting applicationsChiparama · Austin, TX
Full-Time Mid_senior AIARMDDRFPGAPerl
Posted
6d ago
Category
Design
Experience
Mid_senior
Country
United States
About the Role
We are looking for a hands-on SoC Performance Verification Engineer to join our silicon engineering team. You will be responsible for verifying performance characteristics of client-based SoC designs — ensuring throughput, latency, bandwidth, and power targets are met across subsystems before tapeout.
Responsibilities
Develop and execute performance verification plans for client-based SoC subsystems (CPU, GPU, NPU, interconnect, memory subsystem)
Build traffic generators and performance models to stress memory bandwidth, cache coherency, and NoC latency
Define and track KPIs: throughput, IPC, memory latency, bus utilization, power efficiency
Work with RTL and architecture teams to identify performance bottlenecks early in the design cycle
Develop UVM/SystemVerilog testbenches with performance measurement instrumentation
Run performance simulations using industry simulators (VCS, Xcelium, Questa) and analyze waveforms/logs
Collaborate with emulation and FPGA teams for pre-silicon performance validation
Correlate pre-silicon performance results with post-silicon data and ARM Fast Models / Gem5
Write detailed performance analysis reports for architecture and product teams
Required Qualifications
5–10 years of experience in SoC verification or performance engineering
Strong knowledge of client architecture (Cortex-A/M/R series, CMN, CCN, AXI/ACE/CHI protocols)
Hands-on experience with UVM/SystemVerilog performance testbenches
Familiarity with memory subsystem design: DDR, LPDDR, HBM, cache hierarchies
Experience with performance profiling tools and waveform analysis (DVE, Verdi, Simvision)
Proficiency in Python or Perl for automation and result parsing
Strong understanding of NoC, interconnect fabrics, and bandwidth modeling
Nice to Have
Experience with client Fast Models, Gem5, or other architectural simulators
Knowledge of AMBA 5 CHI or CXL protocols
Background in ML/AI accelerator performance verification
Exposure to emulation platforms (Palladium, Veloce, ZeBu)
Prior tapeout experience (7nm/5nm/3nm)
Education
B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science
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We are looking for a hands-on SoC Performance Verification Engineer to join our silicon engineering team. You will be responsible for verifying performance characteristics of client-based SoC designs — ensuring throughput, latency, bandwidth, and power targets are met across subsystems before tapeout.
Responsibilities
Develop and execute performance verification plans for client-based SoC subsystems (CPU, GPU, NPU, interconnect, memory subsystem)
Build traffic generators and performance models to stress memory bandwidth, cache coherency, and NoC latency
Define and track KPIs: throughput, IPC, memory latency, bus utilization, power efficiency
Work with RTL and architecture teams to identify performance bottlenecks early in the design cycle
Develop UVM/SystemVerilog testbenches with performance measurement instrumentation
Run performance simulations using industry simulators (VCS, Xcelium, Questa) and analyze waveforms/logs
Collaborate with emulation and FPGA teams for pre-silicon performance validation
Correlate pre-silicon performance results with post-silicon data and ARM Fast Models / Gem5
Write detailed performance analysis reports for architecture and product teams
Required Qualifications
5–10 years of experience in SoC verification or performance engineering
Strong knowledge of client architecture (Cortex-A/M/R series, CMN, CCN, AXI/ACE/CHI protocols)
Hands-on experience with UVM/SystemVerilog performance testbenches
Familiarity with memory subsystem design: DDR, LPDDR, HBM, cache hierarchies
Experience with performance profiling tools and waveform analysis (DVE, Verdi, Simvision)
Proficiency in Python or Perl for automation and result parsing
Strong understanding of NoC, interconnect fabrics, and bandwidth modeling
Nice to Have
Experience with client Fast Models, Gem5, or other architectural simulators
Knowledge of AMBA 5 CHI or CXL protocols
Background in ML/AI accelerator performance verification
Exposure to emulation platforms (Palladium, Veloce, ZeBu)
Prior tapeout experience (7nm/5nm/3nm)
Education
B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science
Show more Show less