SoC microarchitecture & RTL Design Engineer

Job Description
We are seeking an experienced SoC microarchitecture & RTL Design Engineer with expertise in subsystem-level architecture and RTL development for next-generation high-performance SoCs. The ideal candidate will have hands-on experience designing and developing complex IPs and subsystems for CPU, memory, and interconnect technologies.
Key Responsibilities
Develop subsystem-level microarchitecture (uArch) and RTL for high-performance SoCs.
Design and implement PCIe Gen5/Gen6, DDR5/LPDDR5/LPDDR6, and UCIe 2.0/3.0 subsystems.
Develop and integrate Network-on-Chip (NoC) architectures using Arteris FlexNoC and ARM CMN-700.
Design and integrate ARM Cortex-A, Cortex-R, Cortex-M, and RISC-V CPU subsystems.
Implement SoC clocking, reset, and power management architectures.
Collaborate with architecture, verification, physical design, and validation teams to deliver high-quality RTL.
Participate in design reviews, performance optimization, and silicon bring-up activities.
Required Skills
10-15+ years of experience in SoC Microarchitecture and RTL Design.
Strong hands-on experience with Verilog/SystemVerilog RTL development.
Expertise in one or more of the following:
PCIe Gen5/Gen6
DDR5 / LPDDR5 / LPDDR6
UCIe 2.0 / UCIe 3.0
Arteris FlexNoC / ARM CMN-700
ARM Cortex-A/R/M CPU subsystems
RISC-V subsystems
Strong understanding of Clock, Reset, and Power Management architecture.
Experience with RTL integration, synthesis, timing considerations, and debugging.
Familiarity with ASIC/SoC development flow and scripting (Perl/Python/TCL) is a plus.

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