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SoC Lead / RTL Design Manager
Accepting applicationsBITSILICA · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICEthernetPCIERTLSoC
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
We are looking for an RTL Design Manager to lead high-impact ASIC/SoC development
📍 Location: Bangalore | Hyderabad | Remote
🧑 💼 Experience: 10+ years
Role Title: SoC / Chip Lead – RTL Manager
Minimum Qualifications:
Strong expertise in Ethernet protocols and architecture.
Expertise on PCIE /Ethernet Subsystem Integration.
Experience with Verilog / SystemVerilog RTL design.
Understanding of high-speed interfaces and networking protocols.
Experience with CDC, lint, synthesis, and timing analysis.
Familiarity with AXI / AHB / APB bus protocols.
Strong debugging and problem-solving skills.
If you are interested in this position, please apply to this requisition/ mail us at viswanadha.reddy@bitsilica.com
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📍 Location: Bangalore | Hyderabad | Remote
🧑 💼 Experience: 10+ years
Role Title: SoC / Chip Lead – RTL Manager
Minimum Qualifications:
Strong expertise in Ethernet protocols and architecture.
Expertise on PCIE /Ethernet Subsystem Integration.
Experience with Verilog / SystemVerilog RTL design.
Understanding of high-speed interfaces and networking protocols.
Experience with CDC, lint, synthesis, and timing analysis.
Familiarity with AXI / AHB / APB bus protocols.
Strong debugging and problem-solving skills.
If you are interested in this position, please apply to this requisition/ mail us at viswanadha.reddy@bitsilica.com
Show more Show less