SoC High-Speed Interface Architect

Our Automotive Microcontroller R&D team is looking for an experienced SoC High-Speed Interface Architect to join the Chip-Level Architecture team and own the chip-level integration architecture for high-speed interface PHYs on our next-generation automotive microcontroller platform. This is an SoC architecture role — not an IP design role — focused on how high-speed PHYs land on the chip, meet electrical constraints, and integrate with the platform.

Your role

Key responsibilities in your new role

Own the SoC-level integration architecture for high-speed interface PHYs (LPDDR, Ethernet PHY, HSPHY) — defining placement strategy, power delivery, reference clock assignment, and electrical compliance requirements.
Define and maintain the chip-level interface specifications that high-speed PHY IP teams must comply with, including jitter budgets, termination requirements, and signal integrity constraints.
Serve as the primary SoC architecture interface to PHY IP teams and external PHY vendors — driving integration feasibility assessments and resolving chip-level signal integrity issues.
Perform or oversee early signal integrity simulation and parasitic analysis for high-speed interface regions of the chip.
Review and provide architectural sign-off on PHY IP integration results, floorplan proposals, and high-speed IO region design decisions.
Maintain technical architecture documentation in compliance with ISO 26262 requirements.
Drive datasheet content for high-speed interface electrical parameters in collaboration with IP teams and customers.

Your profile

Qualifications And Skills To Help You Succeed

Bachelor's or Master's degree in Electrical Engineering or related field.
At least 10 years of industry experience in semiconductor development with proven experience in high-speed interface architecture or integration.
Strong knowledge of high-speed interface PHYs — LPDDR memory PHY, Ethernet PHY, and high-speed serial interfaces (HSPHY/SerDes).
Experience with chip-level signal integrity, jitter budgets, and eye diagram analysis for high-speed interfaces.
Understanding of PHY placement constraints, power delivery requirements, and reference clock architecture for high-speed interfaces.
Familiarity with IO ring architecture and ESD protection strategy at high-speed IO boundaries.
Familiarity with ISO 26262 documentation standards.
Pro-active collaborative attitude with strong communication skills in a global multi-cultural team.
Fluent English required; German is a plus.

You are best equipped for this task if you have:

Owned chip-level integration architecture for LPDDR, Ethernet PHY, or high-speed SerDes in a previous SoC program.
Defined jitter budgets, power delivery specs, and placement constraints for high-speed PHYs at the SoC level.
Worked with PHY IP vendors to establish interface specifications, simulation models, and integration acceptance criteria.
Experience distinguishing SoC-level integration constraints from IP-internal design decisions — and driving the former without dictating the latter.
Contributed to datasheet electrical parameters for high-speed interface sections.

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