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SoC Design Verification Engineer (Sensors / CPU / Debug Architecture)
Accepting applicationsBest NanoTech · Bengaluru, Karnataka, India
Full-Time Mid_senior PerlPythonSoCSystemVerilogTcl
Posted
14 Jun
Category
Verification
Experience
Mid_senior
Country
India
5. Required Qualifications 6. Technical Skills
Job Title SoC Design Verification Engineer (Sensors / CPU / Debug Architecture)
Location, Work Mode, Experience Range Location: Bengaluru Work Mode: Onsite Experience: 4 6 Years
Role Overview We are seeking a SoC Design Verification Engineer with experience in sensor interfaces, CPU subsystems, and debug architecture. The role involves developing and executing verification strategies for complex SoC designs. The candidate will work on testbench development, functional verification, and coverage closure across multiple SoC components.
Key Responsibilities
Develop and execute verification plans for SoC components including GPIO, sensors, CPU, and debug architecture
Build and maintain SystemVerilog/UVM-based verification environments
Write and execute test cases to validate functional correctness and corner cases
Perform functional and code coverage analysis and drive coverage closure
Verify eFuse functionality and related configuration flows
Collaborate with design and architecture teams to understand specifications and requirements
Debug simulation failures and identify root causes
Develop reusable verification components and testbench infrastructure
Use scripting for regression automation and test execution
Work with hardware debug tools for issue analysis and validation
Participate in design reviews and verification sign-off discussions
Document verification results and maintain traceability to requirements
B.E / B.Tech / M.E / M.Tech in Electronics, Electrical Engineering, or related field
4 6 years of experience in SoC Design Verification
Verification & Methodology
SoC Design Verification (SoC DV)
Verification planning and coverage-driven verification
Functional verification and coverage analysis
Languages & Methodologies
SystemVerilog
UVM (Universal Verification Methodology)
Domain Expertise
GPIO verification
Sensor interface verification
Debug architecture verification
eFuse verification
Tools & Scripting
Regression automation and scripting (Python / Perl / Tcl)
Simulation and debug tools
Hardware Interaction
Hardware debugging and validation tools
Show more Show less
Job Title SoC Design Verification Engineer (Sensors / CPU / Debug Architecture)
Location, Work Mode, Experience Range Location: Bengaluru Work Mode: Onsite Experience: 4 6 Years
Role Overview We are seeking a SoC Design Verification Engineer with experience in sensor interfaces, CPU subsystems, and debug architecture. The role involves developing and executing verification strategies for complex SoC designs. The candidate will work on testbench development, functional verification, and coverage closure across multiple SoC components.
Key Responsibilities
Develop and execute verification plans for SoC components including GPIO, sensors, CPU, and debug architecture
Build and maintain SystemVerilog/UVM-based verification environments
Write and execute test cases to validate functional correctness and corner cases
Perform functional and code coverage analysis and drive coverage closure
Verify eFuse functionality and related configuration flows
Collaborate with design and architecture teams to understand specifications and requirements
Debug simulation failures and identify root causes
Develop reusable verification components and testbench infrastructure
Use scripting for regression automation and test execution
Work with hardware debug tools for issue analysis and validation
Participate in design reviews and verification sign-off discussions
Document verification results and maintain traceability to requirements
B.E / B.Tech / M.E / M.Tech in Electronics, Electrical Engineering, or related field
4 6 years of experience in SoC Design Verification
Verification & Methodology
SoC Design Verification (SoC DV)
Verification planning and coverage-driven verification
Functional verification and coverage analysis
Languages & Methodologies
SystemVerilog
UVM (Universal Verification Methodology)
Domain Expertise
GPIO verification
Sensor interface verification
Debug architecture verification
eFuse verification
Tools & Scripting
Regression automation and scripting (Python / Perl / Tcl)
Simulation and debug tools
Hardware Interaction
Hardware debugging and validation tools
Show more Show less
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