LT
SoC Design Verification Engineer
Accepting applicationsLorven Technologies Inc. · San Jose, CA
Full-Time Mid_senior AIC++RTLSoCSystemVerilog
Posted
10 Jul
Category
Design
Experience
Mid_senior
Country
United States
Our client is looking SoC Design Verification Engineer for Long Term project in San Jose, CA (Onsite) Below is the detail requirement.
Job Title: SoC Design Verification Enginee
rLocation: San Jose, C
A
Job Descriptio
n:We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality target
s.
Key Responsibiliti
es:Develop and execute SoC-level validation and performance verification strat
egyBuild system-level testbenches, workloads, and performance mod
elsAnalyze performance bottlenecks across CPU, memory, interconnect, and accelerat
orsPerform power and performance trade-off analy
sisCollaborate with architecture, RTL, and software te
amsDebug issues at system level (HW + FW/SW interacti
on)
Required Ski
lls:Strong experience in SoC-level DV / Performance valida
tionUnderstanding of CPU architecture, memory hierarchy, NoC/intercon
nectExpertise in SystemVerilog/UVM + C/C++/Py
thonExperience with performance profiling t
oolsStrong debugging and analytical sk
ills
Good to
Have:Experience in post-silicon validation / bri
ng-upKnowledge of AI/ML or high-performance computing work
loads
Show more Show less
Job Title: SoC Design Verification Enginee
rLocation: San Jose, C
A
Job Descriptio
n:We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality target
s.
Key Responsibiliti
es:Develop and execute SoC-level validation and performance verification strat
egyBuild system-level testbenches, workloads, and performance mod
elsAnalyze performance bottlenecks across CPU, memory, interconnect, and accelerat
orsPerform power and performance trade-off analy
sisCollaborate with architecture, RTL, and software te
amsDebug issues at system level (HW + FW/SW interacti
on)
Required Ski
lls:Strong experience in SoC-level DV / Performance valida
tionUnderstanding of CPU architecture, memory hierarchy, NoC/intercon
nectExpertise in SystemVerilog/UVM + C/C++/Py
thonExperience with performance profiling t
oolsStrong debugging and analytical sk
ills
Good to
Have:Experience in post-silicon validation / bri
ng-upKnowledge of AI/ML or high-performance computing work
loads
Show more Show less