SOC design engineer

Key Responsibilities
Assist in integrating IP blocks and subsystems into the chip top-level RTL.
Develop and maintain top-level Verilog/SystemVerilog files, package files, and configuration scripts.
Support chip-level clock, reset, interrupt, and bus connectivity under the guidance of senior engineers.
Perform RTL compilation, lint, and basic integration checks to identify interface or connectivity issues.
Help maintain chip-level build environments and regression flows.
Work with design and verification teams to resolve integration issues and support regression debugging.
Support chip-level simulation, gate-level simulation, and FPGA/emulation bring-up activities.
Assist with IP version tracking, release integration, and configuration management.
Help prepare integration documentation, block diagrams, and release notes.
Develop simple automation scripts to improve integration efficiency and repetitive tasks.
Participate in design reviews and technical discussions to gain familiarity with SoC architecture and design methodologies.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
1–8 years of experience in ASIC or SoC design, verification, or integration.
Basic knowledge of Verilog or SystemVerilog.
Understanding of digital logic design and computer architecture fundamentals.
Familiarity with Linux development environments and basic scripting (Python, Tcl, Perl, or Shell).
Knowledge of version control systems such as Git or Perforce.
Strong analytical and debugging skills.
Good communication skills and a willingness to learn in a collaborative team environment.
Fluency in both English and Mandarin required as the role involves frequent communication with global teams.
Preferred Qualifications
Exposure to ASIC or FPGA development through coursework, internships, or projects.
Basic understanding of AMBA protocols (AXI, AHB, or APB).
Familiarity with simulation tools such as Synopsys VCS, Siemens QuestaSim, or Cadence Xcelium.
Exposure to lint, CDC, synthesis, or DFT concepts.
Experience using scripting to automate engineering tasks.
Knowledge of ARM- or RISC-V-based SoC architectures is a plus.
Desired Skills
Strong attention to detail.
Ability to learn new tools and methodologies quickly.
Good organizational and time-management skills.
Ability to work effectively in a cross-functional engineering team.
Self-motivated with a proactive approach to problem solving.
Career Growth Opportunities
This role provides hands-on experience across the full ASIC development lifecycle. Engineers will gain exposure to RTL integration, verification, physical design, DFT, timing closure, silicon bring-up, and automation, preparing them for future roles such as Chip Integrator, SoC Design Engineer, or Technical Lead.
Success Metrics
Deliver high-quality chip-level RTL integrations with minimal defects.
Resolve assigned integration issues in a timely manner.
Successfully support chip-level regressions and verification activities.
Demonstrate continuous growth in technical knowledge and engineering independence.
Contribute to automation and process improvements that enhance team productivity.
Show more Show less