SoC Architect - Low Power Design ( HBM)

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build enable everything from AI acceleration and high‑performance computing to next‑generation memory systems. We do it all while committing to integrity, sustainability, and giving back to our communities—fueling the innovation we pursue. 

As a Low Power Architect, you will be a key technical leader within the Heterogeneous Integration Group (HIG), responsible for defining, modeling, and driving SoC‑level power architecture for next‑generation HBM logic die and memory‑centric SoCs. You will work across architecture, RTL, verification, physical design, firmware, and product teams to deliver industry‑leading performance‑per‑watt solutions under aggressive power, thermal, and reliability constraints. 

This role combines system‑level architectural ownership with deep collaboration through implementation and silicon bring‑up. 

Key Responsibilities 

• Define and own SoC‑level low‑power architecture, including power domains, voltage islands, clocking strategies, and low‑power operating modes (active, idle, retention, sleep).  

• Develop power, performance, and thermal models to evaluate architectural tradeoffs and guide PPA optimization across workloads and use cases. 

• Architect and drive implementation of power management features such as DVFS, clock gating, power gating, retention strategies, and adaptive performance controls.  

• Collaborate with SoC and subsystem architects to translate product requirements into power‑aware micro‑architectural specifications. 

• Partner closely with RTL, verification, and physical design teams to ensure correct and efficient implementation of power intent (e.g., UPF/CPF), including debug of power‑related functional and timing issues.  

• Work with firmware and software teams to define hardware‑software power management interfaces, sequencing, and control flows. 

• Drive performance vs. power analysis to support product decisions, roadmap planning, and customer requirements. 

• Support pre‑silicon validation and post‑silicon bring‑up, including silicon power characterization, correlation to models, and root‑cause analysis. 

• Contribute to architectural documentation, design reviews, and cross‑functional technical discussions. 

• Mentor junior architects and engineers, promoting best practices in low‑power design. 

Qualifications 

• Strong experience in SoC or system‑level architecture with a focus on low‑power or energy‑efficient design. 

• Deep understanding of power management techniques: DVFS, power gating, clock gating, voltage regulation, and low‑power state machines.  

• Experience with power modeling, analysis, and trade‑off studies at system and block level.  

• Familiarity with hardware/software interactions impacting power efficiency.  

• Working knowledge of RTL design concepts and low‑power implementation flows (SystemVerilog, UPF/CPF). 

• Experience across the RTL‑to‑GDS flow, including synthesis, STA, and power sign‑off considerations. 

• Strong cross‑functional communication and technical leadership skills. 

• Programming or scripting experience (e.g., Python, C/C++, TCL). 

• Ability to work effectively in a global engineering environment. 

Preferred Qualifications 

• Experience with HBM, DRAM, or memory‑centric SoCs. 

• Background in GPU, CPU, or high‑performance accelerator architectures with aggressive power targets.  

• Familiarity with industry power standards and frameworks (e.g., ARM power management concepts, SCMI‑like interfaces).  

• Exposure to silicon power measurement, lab characterization, or post‑silicon debug. 

• Experience with emulation or prototyping platforms. 

• Master’s or PhD in Electrical Engineering, Computer Engineering, or related field. 

• 10+ years of relevant industry experience, with demonstrated architectural ownership and mentorship.