MC
(SMTS) - SoC Physical Design Engineer,
Accepting applicationsMRL Consulting Group | Global Niche Technology Recruitment · San Jose, CA
Full-Time Mid_senior AICadenceCalibreDFTInnovus
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
SoC Physical Design Engineer
As a Senior SoC Physical Design Engineer, you will lead the physical implementation of complex SoC designs from netlist to GDSII, working closely with RTL, verification, DFT, IP, packaging, and manufacturing teams to deliver high-performance, power-efficient, and area-optimized silicon. This is a hands-on role with ownership of block-level and/or top-level implementation, driving designs through signoff and tapeout across advanced process nodes.
Key Responsibilities:
Own physical implementation for SoC blocks and/or top-level integration, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical optimization to achieve PPA targets.
Drive timing closure across multi-mode, multi-corner (MMMC) scenarios, collaborating with RTL, architecture, and STA teams to resolve setup and hold challenges.
Partner with design and integration teams to implement robust clocking, reset, power, and SoC integration strategies.
Integrate complex IP blocks such as processors, controllers, NoCs, interfaces, PHY-related logic, and DFT structures while ensuring strong timing, power, and physical integrity.
Perform and coordinate physical signoff activities, including DRC, LVS, IR drop, EM, and timing signoff, driving efficient resolution of violations.
Collaborate with packaging, test, and manufacturing teams to ensure designs meet quality, reliability, and manufacturability requirements.
Support tapeout execution, ECO implementation, signoff reviews, and post-silicon correlation activities.
Improve implementation methodologies, flows, and productivity through scripting, automation, and best-practice development.
Required Qualifications:
Extensive experience in SoC physical design implementation from netlist to GDSII on advanced process nodes.
Strong expertise with industry-standard EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
Deep understanding of timing closure, physical optimization, power planning, and power intent methodologies (UPF/CPF).
Experience with hierarchical physical design, top-level integration, partitioning strategies, and large-scale SoC methodologies.
Knowledge of IR drop, electromigration (EM), signal integrity, crosstalk, and noise analysis.
Proven track record of successful tapeouts on advanced foundry technologies.
Strong scripting and automation skills using Python, TCL, Perl, and/or shell.
Preferred Qualifications
Experience with high-performance compute, AI, networking, data center, memory subsystem, or other large-scale SoC architectures.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
15+ years of experience in physical design and implementation.
Can be base in either Folsom, San Jose or Richardson
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As a Senior SoC Physical Design Engineer, you will lead the physical implementation of complex SoC designs from netlist to GDSII, working closely with RTL, verification, DFT, IP, packaging, and manufacturing teams to deliver high-performance, power-efficient, and area-optimized silicon. This is a hands-on role with ownership of block-level and/or top-level implementation, driving designs through signoff and tapeout across advanced process nodes.
Key Responsibilities:
Own physical implementation for SoC blocks and/or top-level integration, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical optimization to achieve PPA targets.
Drive timing closure across multi-mode, multi-corner (MMMC) scenarios, collaborating with RTL, architecture, and STA teams to resolve setup and hold challenges.
Partner with design and integration teams to implement robust clocking, reset, power, and SoC integration strategies.
Integrate complex IP blocks such as processors, controllers, NoCs, interfaces, PHY-related logic, and DFT structures while ensuring strong timing, power, and physical integrity.
Perform and coordinate physical signoff activities, including DRC, LVS, IR drop, EM, and timing signoff, driving efficient resolution of violations.
Collaborate with packaging, test, and manufacturing teams to ensure designs meet quality, reliability, and manufacturability requirements.
Support tapeout execution, ECO implementation, signoff reviews, and post-silicon correlation activities.
Improve implementation methodologies, flows, and productivity through scripting, automation, and best-practice development.
Required Qualifications:
Extensive experience in SoC physical design implementation from netlist to GDSII on advanced process nodes.
Strong expertise with industry-standard EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
Deep understanding of timing closure, physical optimization, power planning, and power intent methodologies (UPF/CPF).
Experience with hierarchical physical design, top-level integration, partitioning strategies, and large-scale SoC methodologies.
Knowledge of IR drop, electromigration (EM), signal integrity, crosstalk, and noise analysis.
Proven track record of successful tapeouts on advanced foundry technologies.
Strong scripting and automation skills using Python, TCL, Perl, and/or shell.
Preferred Qualifications
Experience with high-performance compute, AI, networking, data center, memory subsystem, or other large-scale SoC architectures.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
15+ years of experience in physical design and implementation.
Can be base in either Folsom, San Jose or Richardson
Show more Show less