Silicon Validation Tech Lead – Next-Gen FPGA

The Role


This isn't a contributor role with a senior label on it. We're looking for a technical leader who owns the validation strategy for next-generation FPGA silicon — someone who's been in the lab long enough to know what questions to ask before the silicon even arrives and experienced enough to lead a team through the answers

.
You'll drive bring-up, characterization, and release of cutting-edge FPGA IPs while serving as the technical anchor across design, verification, manufacturing, and test team

s.
What You'll
OwnDefine and lead validation strategy for FPGA IPs — SERDES (PMA/PCS), DDR (DDR4/DDR5/LPDDR4), DPHY, PLL, DSP, MIPI, Fabric,
I/ODrive new silicon bring-up end-to-end — from first power-on through datasheet sign-off and production rele
aseLead a small team of validation engineers as tech lead — set direction, review plans, unblock iss
uesDevelop high-coverage characterization plans; own statistical data analysis and datasheet preparat
ionAuthor test logic RTL and automation frameworks in Python/P
erlBe the central cross-functional resource as silicon moves from arrival to rele
aseSupport customer escalations post-release — own the issue, drive the
fixWhat You Br
ing8+ years in post-silicon or silicon design validat
ionDegree in Electrical Engineering or related fi
eldProven tech lead experience — you've guided a team, not just contributed to
oneDeep expertise in high-speed interface characterization — PCIe, Ethernet, MIPI D-PHY, USB, DisplayPort/HDMI, JESD204, SDI/CoaXpr
essStrong signal integrity and high-speed board design/debug ski
llsProficiency in Verilog/VHDL and FPGA development to
olsTest automation in Python or Perl — you build frameworks, not just scri
ptsExpert-level bench proficiency — BERT, VNA, Oscilloscopes, Protocol Analyz
ersStatistical analysis experience — JMP, R, or equival
entSharp communicator across engineering, manufacturing, and customer-facing te
amsNice to H
aveExperience with FPGA emulation or prototyping environme
ntsBackground in datasheet preparation and IP release methodol

ogy
Loca
tionSan Jose, CA — Onsite, Full-

Time
Why Lat
tice?We're the low power FPGA leader — and our silicon validation team is where product quality is won or lost. You won't be inheriting a steady-state program. You'll be shaping
one.Competitive compensation | Equity | Benefits | High-ownership cu

lture
Lattice Semiconductor is an equal opportunity employer. We encourage candidates from diverse backgrounds to
apply.
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