Silicon Logic Design Engineer

Sr. Logic Design Engineer (8+ years experience)

We are seeking an experienced Logic Design Engineer to join a growing semiconductor engineering team developing advanced memory and high-performance digital IP. The position may be based in San Jose, California or Hillsboro, Oregon, with a hybrid working arrangement.
This role is ideal for an accomplished RTL designer who enjoys owning complex blocks from architectural definition through implementation and integration. You will contribute to the development of next-generation memory subsystem technology for demanding applications including data center, high-performance computing, and artificial intelligence.
As an individual contributor, you will work closely with architecture, verification, physical design, applications, and customer-facing engineering teams. The position offers significant technical ownership and the opportunity to influence architecture, performance, and implementation decisions on advanced semiconductor products.
Employees in office-based positions generally work onsite approximately three days per week, with flexibility to work remotely for the remaining days.
Responsibilities
Define micro-architecture and develop production-quality RTL for complex digital logic blocks.
Design functionality such as scheduling logic, command and transaction pipelines, ordering/coherency mechanisms, control logic, and high-performance system interfaces.
Evaluate performance, power, and area (PPA) trade-offs and use quantitative analysis to guide architectural and implementation decisions.
Partner with design verification engineers to develop verification strategies, identify corner cases, and improve functional coverage.
Collaborate with physical design engineers to address timing closure, power, utilization, and routing/congestion challenges.
Investigate regression failures, perform root-cause analysis, and implement RTL corrections when required.
Participate in design reviews, architecture discussions, and technical problem-solving across engineering disciplines.
Support customer-facing engineering teams during technical evaluations and pre-sales activities.
Assist applications and product engineering teams with integration, deployment, and post-delivery technical issues.
Qualifications
Strong expertise in SystemVerilog and Verilog RTL design.
Extensive experience developing complex ASIC and/or FPGA logic.
Experience with industry-standard simulation environments such as Questa, Xcelium/Incisive, or VCS.
Proficiency with scripting languages such as Python, Perl, and/or Tcl.
Strong understanding of digital design principles, micro-architecture, timing, and hardware implementation.
Ability to independently analyze complex technical problems and drive them to resolution.
Strong written and verbal communication skills and the ability to collaborate effectively across engineering organizations.
Experience managing technical priorities and delivering designs according to project schedules.
Experience
BSEE with 10+ years of relevant ASIC/FPGA logic design experience, or
MSEE with 8+ years of relevant ASIC/FPGA logic design experience.
Experience with memory controllers, high-performance interconnects, cache/coherency architectures, or data-center silicon is highly desirable.
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