Silicon Digital Design Engineer (ASIC / SoC)

Job Title: Silicon DD Engineer
Location: Menlo Park, CA (On-site)
Duration: 12 months Contract to start with

We are seeking a highly motivated Silicon Digital Design Engineer to contribute to the development of advanced ASIC and SoC solutions. This role focuses on digital architecture, RTL design, and SoC integration, supporting the full chip lifecycle from architecture definition through silicon validation and production readiness.

You will work closely with cross-functional teams across architecture, verification, FPGA prototyping, and silicon validation to deliver high-performance, power-efficient designs.

Required Qualifications (Non-Negotiable Skills)
4+ years of experience in Digital Design / ASIC / SoC development
Strong experience in: RTL coding (Verilog/SystemVerilog), SoC integration and architecture and Digital microarchitecture design
Hands-on experience with: Synthesis and timing closure and UPF-based power-aware simulation flows
Experience with UVM/OVM-based verification methodologies
Scripting experience in Python, Tcl, or similar
Solid understanding of ASIC design flow (RTL to GDS)
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent

Preferred Qualifications:
Experience with DFT (Design for Testability) and test program development
Knowledge of high-speed interfaces (PCIe, USB, MIPI, etc.)
Experience with FPGA design and prototyping
Exposure to:
Digital signal processing concepts (fixed/floating point)
Power-aware gate-level simulation flows
Experience working with complex SoC subsystems

Responsibilities:
Contribute to digital microarchitecture definition and development for ASIC/SoC designs
Develop high-quality RTL (Verilog/SystemVerilog) aligned with architecture specifications
Drive SoC integration, including IP integration and subsystem connectivity
Collaborate on verification planning and execution, including UVM-based environments
Support RTL-to-GDSII flow, including synthesis, timing closure, and design optimizations
Work with FPGA teams to enable early prototyping and validation
Assist in chip bring-up, validation, and debug activities through production maturity
Contribute to algorithm analysis, verification, and design improvements
Ensure successful handoff and integration of design blocks into larger systems
Support test planning, debug, and system-level validation efforts
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