H
Signal Integrity/ Power Integrity (SI/PI ) Engineer
Accepting applicationsHCLTech · Sunnyvale, CA
Full-Time Mid_senior CadenceDDREthernetMATLABPCIe
Posted
4d ago
Category
Packaging
Experience
Mid_senior
Country
United States
HCLTech is looking for a highly talented and self- motivated Signal Integrity/ Power Integrity (SI/PI ) Engineer to join it in advancing the technological world through innovation and creativity.
Job Title: Signal Integrity/ Power Integrity (SI/PI ) Engineer
Job REQ ID: 133408
Position Type: Full Time
Location : Sunnyvale CA (Onsite)
Summary
Role Summary
We are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.
Team: Hardware Design Engineering — Advanced Packaging
Key Responsibilities
● Perform SI/PI analysis and design optimization for advanced silicon packages (CoWoS, EMIB, chiplet-based architectures, fan-out wafer-level packaging)
● Develop and validate high-speed channel models for package interconnects including bumps, microbumps, TSVs, RDL layers, and silicon/organic interposers
● Conduct full-wave electromagnetic (EM) simulations of package structures to characterize S-parameters, crosstalk, impedance, and insertion/return loss
● Design and optimize Power Distribution Networks (PDN) — including decoupling strategy, IR drop analysis, and AC impedance profiling from die to board
● Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps)
● Collaborate with IC design, package substrate design, PCB layout, and thermal/mechanical teams to co-optimize package electrical performance
● Develop and correlate simulation models with lab measurements (VNA, TDR, oscilloscope, power noise measurements)
● Define SI/PI design guidelines and constraints for package substrate stackup, routing rules, and bump/via assignments
● Support design-for-manufacturability (DFM) reviews with OSAT partners and substrate vendors
● Investigate and resolve SI/PI-related failures during silicon bring-up and validation phases
Required Qualifications
● 5+ years of experience in SI/PI analysis for semiconductor packaging or high-speed PCB design
● Strong proficiency with industry-standard EM and circuit simulation tools:
EM Solvers: Ansys HFSS, Ansys SIwave, Cadence Clarity 3D, Keysight ADS Momentum
Circuit Simulation: Synopsys HSPICE, Cadence Spectre, Keysight ADS
PDN Analysis: Ansys RedHawk, Cadence Voltus, Sigrity PowerDC/PowerSI
● Deep understanding of transmission line theory, Maxwell's equations, and S-parameter analysis
● Experience with high-speed interface protocols (PCIe, UCIe, HBM, DDR, Ethernet SerDes)
● Proficiency in package stackup design, impedance control, and via transition optimization
● Hands-on experience with measurement correlation (VNA, TDR/TDT, near-field scanning)
● Programming/scripting skills (Python, MATLAB, Tcl) for automation and post-processing
Preferred Qualifications
● Experience with 2.5D/3D advanced packaging technologies (CoWoS, EMIB, Foveros, hybrid bonding)
● Familiarity with chiplet-based disaggregated architectures and die-to-die interconnect standards (UCIe, BoW)
● Knowledge of co-simulation methodologies (chip-package-board co-design)
● Experience with statistical analysis and Monte Carlo methods for manufacturing variation impact
● Understanding of thermal-aware electrical analysis (electro-thermal co-simulation)
● Contributions to IEEE/DesignCon publications or industry standards committees (JEDEC, OIF, UCIe Consortium)
● Experience working with OSATs (ASE, Amkor, TSMC InFO/CoWoS) and substrate vendors
Pay and Benefits
Pay Range Minimum: $87000/annum
Pay Range Maximum: $172000/annum
HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to secure@hcltech.com for investigation.
A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year
How You’ll Grow
At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best
you best
Show more Show less
Job Title: Signal Integrity/ Power Integrity (SI/PI ) Engineer
Job REQ ID: 133408
Position Type: Full Time
Location : Sunnyvale CA (Onsite)
Summary
Role Summary
We are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.
Team: Hardware Design Engineering — Advanced Packaging
Key Responsibilities
● Perform SI/PI analysis and design optimization for advanced silicon packages (CoWoS, EMIB, chiplet-based architectures, fan-out wafer-level packaging)
● Develop and validate high-speed channel models for package interconnects including bumps, microbumps, TSVs, RDL layers, and silicon/organic interposers
● Conduct full-wave electromagnetic (EM) simulations of package structures to characterize S-parameters, crosstalk, impedance, and insertion/return loss
● Design and optimize Power Distribution Networks (PDN) — including decoupling strategy, IR drop analysis, and AC impedance profiling from die to board
● Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps)
● Collaborate with IC design, package substrate design, PCB layout, and thermal/mechanical teams to co-optimize package electrical performance
● Develop and correlate simulation models with lab measurements (VNA, TDR, oscilloscope, power noise measurements)
● Define SI/PI design guidelines and constraints for package substrate stackup, routing rules, and bump/via assignments
● Support design-for-manufacturability (DFM) reviews with OSAT partners and substrate vendors
● Investigate and resolve SI/PI-related failures during silicon bring-up and validation phases
Required Qualifications
● 5+ years of experience in SI/PI analysis for semiconductor packaging or high-speed PCB design
● Strong proficiency with industry-standard EM and circuit simulation tools:
EM Solvers: Ansys HFSS, Ansys SIwave, Cadence Clarity 3D, Keysight ADS Momentum
Circuit Simulation: Synopsys HSPICE, Cadence Spectre, Keysight ADS
PDN Analysis: Ansys RedHawk, Cadence Voltus, Sigrity PowerDC/PowerSI
● Deep understanding of transmission line theory, Maxwell's equations, and S-parameter analysis
● Experience with high-speed interface protocols (PCIe, UCIe, HBM, DDR, Ethernet SerDes)
● Proficiency in package stackup design, impedance control, and via transition optimization
● Hands-on experience with measurement correlation (VNA, TDR/TDT, near-field scanning)
● Programming/scripting skills (Python, MATLAB, Tcl) for automation and post-processing
Preferred Qualifications
● Experience with 2.5D/3D advanced packaging technologies (CoWoS, EMIB, Foveros, hybrid bonding)
● Familiarity with chiplet-based disaggregated architectures and die-to-die interconnect standards (UCIe, BoW)
● Knowledge of co-simulation methodologies (chip-package-board co-design)
● Experience with statistical analysis and Monte Carlo methods for manufacturing variation impact
● Understanding of thermal-aware electrical analysis (electro-thermal co-simulation)
● Contributions to IEEE/DesignCon publications or industry standards committees (JEDEC, OIF, UCIe Consortium)
● Experience working with OSATs (ASE, Amkor, TSMC InFO/CoWoS) and substrate vendors
Pay and Benefits
Pay Range Minimum: $87000/annum
Pay Range Maximum: $172000/annum
HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to secure@hcltech.com for investigation.
A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year
How You’ll Grow
At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best
you best
Show more Show less