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Senior Verification Lead
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru South, Karnataka, India
Full-Time Mid_senior UVMSystemVerilogVerificationFunctional Verification
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise across the entire chip development lifecycle. Founded in 2018, the company has become a trusted partner for global semiconductor organizations, providing high-quality design and verification services tailored to product-driven teams. With engineering centers in India and Canada, LeadIC delivers solutions spanning custom, memory and analog layout, mixed-signal circuit design, digital RTL, design verification, physical design, STA, DFT, and IP characterization. The company emphasizes strong engineering ownership, rigorous quality practices, and flexible engagement models that support scalable offshore and ODC teams. LeadIC focuses on building long-term technical partnerships that enable customers to achieve predictable, high-performance silicon outcomes.
Role Description The Senior Verification Lead will own and drive verification activities for complex digital and mixed-signal SoCs and IP blocks, ensuring functional correctness and high-quality tape-out. This full-time hybrid role is based in Bengaluru South, with flexibility for partial work from home as per project needs. Day-to-day responsibilities include defining verification plans, architecting UVM-based environments, developing testbenches and stimuli, writing and reviewing test cases, and driving coverage closure. The Senior Verification Lead will guide and mentor verification engineers, review their deliverables, and coordinate with design, physical design, and firmware teams to resolve issues and align on specifications. The role also involves contributing to methodology improvements, managing schedules and risks, supporting customer communication, and ensuring adherence to structured, quality-driven execution practices.
Qualifications
Strong expertise in design verification methodologies, including UVM, SystemVerilog-based environments, and constrained random verification.
Experience in mixed-signal and AMS verification, and familiarity with full-chip integration and regression strategies.
Solid understanding of digital design concepts, RTL development flows, micro-architecture, and interface protocols (e.g., AXI, PCIe, DDR).
Hands-on experience with industry-standard EDA tools for simulation, debug, coverage analysis, and waveform inspection.
Proficiency in scripting (e.g., Python, Perl, Shell) for automation, regression management, and data analysis.
Demonstrated ability to lead verification teams, mentor junior engineers, and coordinate cross-functional technical discussions.
Strong analytical, problem-solving, and debugging skills, with a structured approach to root-cause analysis and issue resolution.
Clear and concise communication skills, including specification review, documentation, and effective collaboration with global teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
Experience in VLSI product companies or service organizations
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Role Description The Senior Verification Lead will own and drive verification activities for complex digital and mixed-signal SoCs and IP blocks, ensuring functional correctness and high-quality tape-out. This full-time hybrid role is based in Bengaluru South, with flexibility for partial work from home as per project needs. Day-to-day responsibilities include defining verification plans, architecting UVM-based environments, developing testbenches and stimuli, writing and reviewing test cases, and driving coverage closure. The Senior Verification Lead will guide and mentor verification engineers, review their deliverables, and coordinate with design, physical design, and firmware teams to resolve issues and align on specifications. The role also involves contributing to methodology improvements, managing schedules and risks, supporting customer communication, and ensuring adherence to structured, quality-driven execution practices.
Qualifications
Strong expertise in design verification methodologies, including UVM, SystemVerilog-based environments, and constrained random verification.
Experience in mixed-signal and AMS verification, and familiarity with full-chip integration and regression strategies.
Solid understanding of digital design concepts, RTL development flows, micro-architecture, and interface protocols (e.g., AXI, PCIe, DDR).
Hands-on experience with industry-standard EDA tools for simulation, debug, coverage analysis, and waveform inspection.
Proficiency in scripting (e.g., Python, Perl, Shell) for automation, regression management, and data analysis.
Demonstrated ability to lead verification teams, mentor junior engineers, and coordinate cross-functional technical discussions.
Strong analytical, problem-solving, and debugging skills, with a structured approach to root-cause analysis and issue resolution.
Clear and concise communication skills, including specification review, documentation, and effective collaboration with global teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
Experience in VLSI product companies or service organizations
Show more Show less