VL
Senior Verification Engineer
Accepting applicationsVibotek LLC · Austin, United States, North America
Full-Time Senior AIAnalogEthernetSystemVerilogUVM
Posted
20 Mar
Category
Verification
Experience
Senior
Country
United States
Domain Information technology (IT)
Location USA - Austin
Status Active
=======================================
Senior Verification Engineer
Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP (digital
signal processing) solutions for cloud and AI infrastructure, a foundational technology that enables
faster and more efficient transmission within and between AI data centers. The firm is empowering
the future of AI infrastructure and cloud connectivity with DSP innovations. The firm recently came
out of stealth with $180MM funding and is backed by storied venture investors including Kleiner
Perkins, Spark Capital, Mayfield and Fidelity Investments.
Responsibilities
Location USA - Austin
Status Active
=======================================
Senior Verification Engineer
Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP (digital
signal processing) solutions for cloud and AI infrastructure, a foundational technology that enables
faster and more efficient transmission within and between AI data centers. The firm is empowering
the future of AI infrastructure and cloud connectivity with DSP innovations. The firm recently came
out of stealth with $180MM funding and is backed by storied venture investors including Kleiner
Perkins, Spark Capital, Mayfield and Fidelity Investments.
Responsibilities
- Plan and perform the verification of digital design blocks according to the design specification
- Build verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for corner-cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrices to close the full functionality.
- 10+ years of experience; At least 7 years of experience in verification - a must.
- In depth knowledge in VLSI verification flow, languages and concepts - a must. Performed
- Deep experience in building verification environments using SystemVerilog and UVM or
- Performed at last 2 or more full block/system verification cycles.
- Experience in data path or data protocols, specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM, UVM, OVM).
- Trackrecord in identifying and written all types of coverage measures for corner-cases.
- Planned and performed the verification of digital design blocks according to the design
- Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative
- Communication: Strong communication skills, including the ability to write test plans, present
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