RC
Senior Verification Engineer – ASIC
Accepting applicationsRecvisor Consultants · Greater Bengaluru Area
Full-Time Mid_senior ASICATPGDFTFPGAMixed-Signal
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
India
Job Summary
We are looking for an experienced Senior ASIC Verification Engineer with strong expertise in block-level, subsystem-level, and chip-level verification for mixed-signal devices. The ideal candidate should have extensive hands-on experience in SystemVerilog, UVM, scripting, debugging, and verification methodologies, along with the ability to collaborate effectively with cross-functional engineering teams.
Key Responsibilities
Perform ASIC verification at block, subsystem, and chip top levels.
Develop and maintain verification environments using SystemVerilog and UVM.
Create, execute, and debug verification test cases for digital and mixed-signal designs.
Work closely with design engineers to understand design updates and implement corresponding verification changes.
Develop reusable verification components and environments.
Implement and analyze Register Abstraction Layer (RAL), functional coverage, and code coverage.
Perform gate-level simulations across multiple PVT (Process, Voltage, Temperature) corners.
Generate VCD files for power analysis.
Work with DFT concepts and execute ATPG simulations.
Collaborate with analog and architecture teams for netlist and model integration into the verification environment.
Support FPGA-based validation, silicon bring-up, and characterization activities.
Debug design and verification environment issues efficiently.
Support customer issue analysis and debug activities when required.
Use scripting languages such as Perl, Python, and Shell for automation.
Manage multiple verification tasks while ensuring timely delivery.
Collaborate effectively within cross-functional teams in a fast-paced development environment.
Required Skills
Strong understanding of Digital Design fundamentals.
Hands-on experience with SystemVerilog and UVM.
Expertise in ASIC verification methodologies.
Experience with Mixed-Signal ASIC verification.
Knowledge of RAL, Functional Coverage, and Code Coverage.
Experience with Gate-Level Simulation (GLS) and PVT validation.
Good understanding of DFT and ATPG simulations.
Proficiency in Perl, Python, and Shell scripting.
Experience with FPGA-based validation, silicon bring-up, and characterization.
Strong debugging, analytical, communication, and time management skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related technology discipline.
8–15 years of hands-on experience in ASIC Verification.
Proven experience working on Mixed-Signal devices.
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We are looking for an experienced Senior ASIC Verification Engineer with strong expertise in block-level, subsystem-level, and chip-level verification for mixed-signal devices. The ideal candidate should have extensive hands-on experience in SystemVerilog, UVM, scripting, debugging, and verification methodologies, along with the ability to collaborate effectively with cross-functional engineering teams.
Key Responsibilities
Perform ASIC verification at block, subsystem, and chip top levels.
Develop and maintain verification environments using SystemVerilog and UVM.
Create, execute, and debug verification test cases for digital and mixed-signal designs.
Work closely with design engineers to understand design updates and implement corresponding verification changes.
Develop reusable verification components and environments.
Implement and analyze Register Abstraction Layer (RAL), functional coverage, and code coverage.
Perform gate-level simulations across multiple PVT (Process, Voltage, Temperature) corners.
Generate VCD files for power analysis.
Work with DFT concepts and execute ATPG simulations.
Collaborate with analog and architecture teams for netlist and model integration into the verification environment.
Support FPGA-based validation, silicon bring-up, and characterization activities.
Debug design and verification environment issues efficiently.
Support customer issue analysis and debug activities when required.
Use scripting languages such as Perl, Python, and Shell for automation.
Manage multiple verification tasks while ensuring timely delivery.
Collaborate effectively within cross-functional teams in a fast-paced development environment.
Required Skills
Strong understanding of Digital Design fundamentals.
Hands-on experience with SystemVerilog and UVM.
Expertise in ASIC verification methodologies.
Experience with Mixed-Signal ASIC verification.
Knowledge of RAL, Functional Coverage, and Code Coverage.
Experience with Gate-Level Simulation (GLS) and PVT validation.
Good understanding of DFT and ATPG simulations.
Proficiency in Perl, Python, and Shell scripting.
Experience with FPGA-based validation, silicon bring-up, and characterization.
Strong debugging, analytical, communication, and time management skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related technology discipline.
8–15 years of hands-on experience in ASIC Verification.
Proven experience working on Mixed-Signal devices.
Show more Show less