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Senior Validation Engineer
Accepting applicationsWipro · Bengaluru, Karnataka, India
Full-Time Mid_senior EthernetMentorPCIePythonSerDes
Estimated market salary
₹7-12 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
22h ago
Category
Verification
Experience
Mid_senior
Country
India
· Hands-on expertise in Ethernet validation (1G/10G/25G/50G/100G+), link bring-up, throughput, latency, packet integrity, and interoperability testing.
· Experience in USB 3.x/USB4 validation, Type-C, Power Delivery (PD), compliance, functional, and stress testing.
· Strong understanding of HSIO/SerDes architecture, signal integrity, equalization, jitter, eye-diagram analysis, and lane margining.
· Experience in post-silicon validation, platform bring-up, and hardware-software integration testing.
· Knowledge of PCIe, Ethernet, and USB protocol analyzers and debug methodologies.
· Hands-on experience with Oscilloscopes, BERTs, Protocol Analyzers, Logic Analyzers, Traffic Generators, and Network Test Equipment.
· Experience debugging issues across Silicon, BIOS/UEFI, Firmware, Driver, and Linux/Windows OS layers.
· Proficiency in Python, Shell scripting, and test automation frameworks.
· Experience with compliance and interoperability testing using industry standards and certification tools.
· Familiarity with CXL, NVMe, RDMA, DPDK, SR-IOV, and virtualization technologies.
· Strong understanding of server architecture, x86 platforms, and data center technologies.
Key Responsibilities
· Develop and execute validation plans for PCIe, Ethernet, USB, and HSIO IPs.
· Perform functional, stress, performance, compliance, and interoperability testing.
· Analyze protocol captures, SI measurements, and hardware logs to identify root causes.
· Validate power management features, error handling, and recovery mechanisms.
· Collaborate with Design, Firmware, BIOS, Driver, and Architecture teams to resolve issues.
· Automate validation workflows and improve test coverage using Python-based frameworks.
· Mentor junior engineers and provide technical leadership for validation activities.
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· Experience in USB 3.x/USB4 validation, Type-C, Power Delivery (PD), compliance, functional, and stress testing.
· Strong understanding of HSIO/SerDes architecture, signal integrity, equalization, jitter, eye-diagram analysis, and lane margining.
· Experience in post-silicon validation, platform bring-up, and hardware-software integration testing.
· Knowledge of PCIe, Ethernet, and USB protocol analyzers and debug methodologies.
· Hands-on experience with Oscilloscopes, BERTs, Protocol Analyzers, Logic Analyzers, Traffic Generators, and Network Test Equipment.
· Experience debugging issues across Silicon, BIOS/UEFI, Firmware, Driver, and Linux/Windows OS layers.
· Proficiency in Python, Shell scripting, and test automation frameworks.
· Experience with compliance and interoperability testing using industry standards and certification tools.
· Familiarity with CXL, NVMe, RDMA, DPDK, SR-IOV, and virtualization technologies.
· Strong understanding of server architecture, x86 platforms, and data center technologies.
Key Responsibilities
· Develop and execute validation plans for PCIe, Ethernet, USB, and HSIO IPs.
· Perform functional, stress, performance, compliance, and interoperability testing.
· Analyze protocol captures, SI measurements, and hardware logs to identify root causes.
· Validate power management features, error handling, and recovery mechanisms.
· Collaborate with Design, Firmware, BIOS, Driver, and Architecture teams to resolve issues.
· Automate validation workflows and improve test coverage using Python-based frameworks.
· Mentor junior engineers and provide technical leadership for validation activities.
Show more Show less