Senior Staff Physical Design Engineer

Location: Bangalore
Job Summary
We are looking for an experienced Physical Design Engineer (10-14 Years) with strong expertise in RTL-to-GDS implementation, Cadence Innovus, advanced-node Block/SoC designs, and PPA optimization. Candidates should have hands-on System Verilog + Python/Perl scripting experience and a proven track record of delivering high-volume shipped products.

What You'll Drive & Bring to the Role
Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes
Expertise and experience with industry-standard CAD tools from Cadence-Innovus.
Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.
Expert knowledge of System Verilog, as well as Perl, Python or other scripting languages.
Worked at Subsystem level and good experience at Hierarchy block/s.
Proven track record of execution on products which have shipped in high-volume.

Required Qualifications
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline with 8-10 yrs of work experience.

skills:
Innovus
SoC
Tempus
Genus
Voltus
redhawk

Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
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