PA
Senior/ Staff Memory Layout Engineer
Accepting applicationsProdapt ASIC services (Formerly Innovative Logic) · Bengaluru, Karnataka, India
Full-Time Mid_senior Memory LayoutSRAMCustom LayoutCadence VirtuosoCalibre
Estimated market salary
₹59-106 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
About Prodapt
Prodapt is a global leader in the "Connectedness" industry and a certified Great Place To Work®. We are part of the 130-year-old Jhaver Group, a conglomerate with over 32,000 employees. Our ASIC & Semiconductor division (formerly Innovative Logic) is a powerhouse in SoC design, focusing on advanced nodes (down to 3nm) for 5G, AI, IoT, and Cloud sectors.
The Role
We are seeking a Memory Layout Engineer to drive the custom layout design of memory blocks. You will collaborate with circuit design teams to ensure performance, area, and reliability targets are met using the latest FinFET technologies.
Key Responsibilities
Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
Execute and verify DRC/LVS checks and parasitic extraction.
Optimize layouts for area and performance in collaboration with circuit designers.
Apply expertise in deep submicron and FinFET technologies.
Required Qualifications
Experience: 4+ years in Memory Layout design
Technical Skills: Mastery of Cadence Virtuoso and Calibre/Assura
Node Expertise: Hands-on experience with 2nm to 7nm TSMC processes
Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field
Show more Show less
Prodapt is a global leader in the "Connectedness" industry and a certified Great Place To Work®. We are part of the 130-year-old Jhaver Group, a conglomerate with over 32,000 employees. Our ASIC & Semiconductor division (formerly Innovative Logic) is a powerhouse in SoC design, focusing on advanced nodes (down to 3nm) for 5G, AI, IoT, and Cloud sectors.
The Role
We are seeking a Memory Layout Engineer to drive the custom layout design of memory blocks. You will collaborate with circuit design teams to ensure performance, area, and reliability targets are met using the latest FinFET technologies.
Key Responsibilities
Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
Execute and verify DRC/LVS checks and parasitic extraction.
Optimize layouts for area and performance in collaboration with circuit designers.
Apply expertise in deep submicron and FinFET technologies.
Required Qualifications
Experience: 4+ years in Memory Layout design
Technical Skills: Mastery of Cadence Virtuoso and Calibre/Assura
Node Expertise: Hands-on experience with 2nm to 7nm TSMC processes
Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field
Show more Show less