Senior Staff Engineer – Physical Design

Senior Staff Engineer – Physical Design
Location: Bengaluru
Experience: 10–16 Years
Function: Physical Design / ASIC
Role Overview
We are looking for a Senior Staff Engineer – Physical Design to drive full-chip physical implementation for advanced SoC designs. The role requires deep hands-on expertise across RTL-to-GDSII, timing closure, physical optimization, and signoff.
Key Responsibilities
Own full-chip physical design from synthesis through P&R, timing closure and tapeout.
Drive floorplanning, power planning, placement, CTS, routing and physical optimization.
Lead STA, MCMM timing closure, ECO implementation and signoff.
Analyze and resolve setup/hold, congestion, IR drop, EM, DRC/LVS and SI issues.
Drive synthesis, PPA optimization and physical-aware implementation.
Work closely with RTL, STA, DFT, PD and signoff teams to resolve critical design issues.
Develop and optimize PD flows, methodologies and automation scripts using Tcl/Python/Perl.
Provide technical leadership on complex blocks/full-chip designs and mentor senior engineers.
Core Technical Skills
Strong hands-on expertise in ASIC Physical Design / Full-Chip Implementation.
Expertise in Synopsys ICC2/FC, PrimeTime, Design Compiler or equivalent tools.
Strong understanding of STA, MCMM, CTS, timing closure and ECOs.
Experience with advanced-node SoCs, high-performance designs and complex clocking.
Strong knowledge of UPF/low-power implementation, IR/EM and physical signoff.
Proficiency in Tcl/Python/Perl scripting and flow automation.
Strong understanding of PPA trade-offs, congestion optimization and design closure.
Preferred
Experience with 5nm/4nm/3nm or advanced process nodes.
Proven ownership of full-chip tapeout and complex timing closure.
Strong problem-solving, technical leadership and cross-functional collaboration skills.
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