BS
Senior/Staff Engineer, ASIC Design
Accepting applicationsBlack Sesame Technologies Inc · San Jose, CA
Full-Time Mid_senior AIASICC++EthernetPCIE
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
About Black Sesame Technologies
Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading provider of AI system-on-chip solutions. Our mass-produced AI chips are deployed across the automotive and robotics markets, delivering high-performance, automotive-grade computing solutions at scale. As we develop our next generation of AI inference accelerators, we are rapidly expanding our R&D teams in Singapore and the United States. Join us and help build the foundational technologies powering the future of intelligent machines.
Responsibilities
1. Develope micro-architecture for High Speed IO design
2. RTL design, verification and integration
3. Synthesis and optimize for timing, area and power
4. Module and top-level documentation
5. Work with architecture and software teams to develop next-generation silicon.
Basic Qualifications
1. Master's degree and above in Electrical/Electronics/Computer Engineering， 5+ years experience.
2. Fluent with HDL languages(Verilog, SystemVerilog)
3. Experience in High Speed IO such as PCIE, Die to Die, Chip to Chip, Ethernet and etc
4. Familiar with software languages C/C++
5. Familiar with EDA tools and CAD flow
6. Good documentation skill
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Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading provider of AI system-on-chip solutions. Our mass-produced AI chips are deployed across the automotive and robotics markets, delivering high-performance, automotive-grade computing solutions at scale. As we develop our next generation of AI inference accelerators, we are rapidly expanding our R&D teams in Singapore and the United States. Join us and help build the foundational technologies powering the future of intelligent machines.
Responsibilities
1. Develope micro-architecture for High Speed IO design
2. RTL design, verification and integration
3. Synthesis and optimize for timing, area and power
4. Module and top-level documentation
5. Work with architecture and software teams to develop next-generation silicon.
Basic Qualifications
1. Master's degree and above in Electrical/Electronics/Computer Engineering， 5+ years experience.
2. Fluent with HDL languages(Verilog, SystemVerilog)
3. Experience in High Speed IO such as PCIE, Die to Die, Chip to Chip, Ethernet and etc
4. Familiar with software languages C/C++
5. Familiar with EDA tools and CAD flow
6. Good documentation skill
Show more Show less