QI

Senior Staff Circuit Design Engineer

Accepting applications

Quintessent Inc. · San Francisco Bay Area

Full-Time Mid_senior AIATECadenceDFTRTL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Build the laser platform that powers the next generation of AI infrastructure.
Quintessent is taking on some of the hardest challenges in optical connectivity – directly
attacking the foundational bottlenecks limiting the scalability and reliability of next-generation AI
and computing infrastructure. Our team has trailblazed pioneering work in quantum dot lasers
and amplifiers, heterogeneous integration, and multi-wavelength silicon photonics. We are
converging innovations in materials science, process integration, chip and system design to
build products that we believe will form a core part of AI networking systems.

We are a scrappy, high-trust team that takes ownership, stays humble, and believes in tackling
hard problems with speed, intellectual honesty, and relentless improvement. We hold ourselves
to a high bar, start from a deep understanding of our customers’ problems, and win or lose
together. If this sounds like you, and you want to build the laser and electronics platform that powers the next generation of AI infrastructure, we’d love to talk.
We are looking for a senior circuit design engineer to build the next generation of pluggable optical interconnects for Scale-Up and Scale-Out Data Center Interconnect Products

You will be the technical authority developing firmware for products, responsible for:
Building and/or selecting electronics for optical interconnected products. These include compensation circuits for silicon photonics, and driver and TIAs. Developing circuits for next generation DWDM based WPO (Wide and Parallel Optical Interconnects).

Your work will directly shape the products that ship and the capabilities the company builds.

To succeed, you will need these qualifications:

B.S. or M.S. in Electrical engineering.
Must have strong analog design expertise.
Experience with high-speed SerDes, PLL, ADC, DAC design.
Experience in optical Driver, TIA design is an asset.
Ability to work from specification to block diagram. schematic capture, layout reviews, and associated monte-carlo simulations.
Hands on experience in using Cadence tools to generate, simulate, and assemble unit level blocks, and assembling top level blocks in hierarchical tools flows. Work closely with layout engineer, RTL engineer, and firmware engineers.
Knowledge of DFT tool flow for high-speed circuits and associated ATE, and systems testing is an asset. Ability to bring up the blocks in time and put a plan for silicon bring up for production devices

Bonus if you’ve also:
Supported high-volume production
Worked directly with customers or partners

For more questions or to apply for the position, contact: hiring@quintessent.com
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