SI
Senior Staff Analog Design Engineer- 16906
Accepting applicationsSynopsys Inc · Sunnyvale, CA
Full-Time Mid_senior AIAnalogMentorPCIeSerDes
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years designing analog circuits that perform reliably in production silicon, not just in simulation. You understand that architectural decisions made early determine whether a transceiver meets its power and performance targets. Reading D2D standards like UCIe, you identify opportunities where circuit innovation can recover area or power. You have debugged post-silicon issues, presented technical results to customers, and know that layout planning is integral to circuit performance. Mentoring engineers comes naturally to you, and you take pride in building team capability while delivering results.
What You'll Be Doing
Develop transceiver architectures and sub-block specifications based on UCIe and D2D standards
Design analog circuits for high-speed Die-to-Die interconnect IP, including clock recovery, equalization, and bias blocks
Conduct system modeling, margin analysis, and jitter budgeting to validate design robustness
Oversee PHY-level layout to minimize parasitics and process variation impact
Present simulation results to internal teams, customers, and industry forums
Analyze post-silicon data and propose design enhancements
Mentor global design team members and conduct technical design reviews
The Impact You Will Have
Define architectures that deliver significant improvements in power, area, and performance for chiplet interconnects
Enable customer success by delivering production-ready Die-to-Die IP
Reduce design cycle time through streamlined verification and design methodologies
Influence industry direction through technical engagement and standards participation
Build design expertise across the global organization
Accelerate customer time-to-market with reliable, high-margin IP solutions
What You'll Need
Bachelor's or Master's degree in Electrical Engineering with 8+ years of analog circuit design experience
Expertise in high-speed transceiver design including SerDes or D2D interfaces
Strong foundation in system modeling, jitter analysis, and margin budgeting
Proven experience taking circuits from architecture through post-silicon validation
Familiarity with industry standards such as UCIe or PCIe
Experience collaborating across distributed, cross-functional teams
Who You Are
You identify architectural issues quickly and communicate solutions clearly
You consider layout and parasitics during schematic design
You present complex technical trade-offs effectively to customers and leadership
You mentor engineers with patience and clarity
You prioritize design margin over schedule pressure when necessary
You stay current on industry trends and emerging technologies
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards And Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years designing analog circuits that perform reliably in production silicon, not just in simulation. You understand that architectural decisions made early determine whether a transceiver meets its power and performance targets. Reading D2D standards like UCIe, you identify opportunities where circuit innovation can recover area or power. You have debugged post-silicon issues, presented technical results to customers, and know that layout planning is integral to circuit performance. Mentoring engineers comes naturally to you, and you take pride in building team capability while delivering results.
What You'll Be Doing
Develop transceiver architectures and sub-block specifications based on UCIe and D2D standards
Design analog circuits for high-speed Die-to-Die interconnect IP, including clock recovery, equalization, and bias blocks
Conduct system modeling, margin analysis, and jitter budgeting to validate design robustness
Oversee PHY-level layout to minimize parasitics and process variation impact
Present simulation results to internal teams, customers, and industry forums
Analyze post-silicon data and propose design enhancements
Mentor global design team members and conduct technical design reviews
The Impact You Will Have
Define architectures that deliver significant improvements in power, area, and performance for chiplet interconnects
Enable customer success by delivering production-ready Die-to-Die IP
Reduce design cycle time through streamlined verification and design methodologies
Influence industry direction through technical engagement and standards participation
Build design expertise across the global organization
Accelerate customer time-to-market with reliable, high-margin IP solutions
What You'll Need
Bachelor's or Master's degree in Electrical Engineering with 8+ years of analog circuit design experience
Expertise in high-speed transceiver design including SerDes or D2D interfaces
Strong foundation in system modeling, jitter analysis, and margin budgeting
Proven experience taking circuits from architecture through post-silicon validation
Familiarity with industry standards such as UCIe or PCIe
Experience collaborating across distributed, cross-functional teams
Who You Are
You identify architectural issues quickly and communicate solutions clearly
You consider layout and parasitics during schematic design
You present complex technical trade-offs effectively to customers and leadership
You mentor engineers with patience and clarity
You prioritize design margin over schedule pressure when necessary
You stay current on industry trends and emerging technologies
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards And Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less