BN
Senior SoC Verification Engineer – UVM DDR
Accepting applicationsBest NanoTech · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceDDREthernetMentorPCIe
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Job Title - Senior SoC Verification Engineer – UVM DDR2. Location, Work Mode, Experience Range
Location: India (Bangalore)
Work Mode: Hybrid / Onsite
Experience: 4–5 Years
Role Overview
The role focuses on SoC-level verification with emphasis on DDR memory subsystems. The candidate will be responsible for developing and executing UVM-based verification environments, ensuring functional correctness, and achieving coverage closure. The position requires strong debugging skills and hands-on experience with DDR protocols.
Key Responsibilities
Develop and maintain UVM-based verification environments for DDR subsystems
Create and execute detailed verification test plans
Design and implement testbench components using SystemVerilog and UVM
Develop stimulus using C/Assembly where required
Perform assertion-based verification for protocol compliance
Drive coverage-driven verification and achieve coverage closure targets
Analyze simulation results and debug functional issues using waveforms
Collaborate with design teams to understand architecture and resolve issues
Review test plans, verification strategies, and testcases
Automate verification flows using scripting languages
Work with industry-standard simulators for regression and debug
Contribute to continuous improvement of verification methodologies
Required Qualifications
Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
4–5 years of experience in SoC verification
Strong experience in DDR protocol verification (DDR4/DDR5/LPDDR)
Proven experience in coverage closure and verification sign-off
Technical Skills & Languages
SystemVerilog, Verilog
C / Assembly (for stimulus generation)
Verification Methodologies
UVM (Universal Verification Methodology)
Assertion-Based Verification (ABV)
Coverage-Driven Verification
Protocols
DDR (DDR4, DDR5, LPDDR)
Exposure to PCIe / USB / Ethernet (optional)
Tools & Simulators
Synopsys VCS
Cadence Xcelium
Mentor Questa
Debug & Analysis
Waveform debugging
Functional debugging and root cause analysis
Scripting & Automation
Python / Perl / Shell scripting
Show more Show less
Location: India (Bangalore)
Work Mode: Hybrid / Onsite
Experience: 4–5 Years
Role Overview
The role focuses on SoC-level verification with emphasis on DDR memory subsystems. The candidate will be responsible for developing and executing UVM-based verification environments, ensuring functional correctness, and achieving coverage closure. The position requires strong debugging skills and hands-on experience with DDR protocols.
Key Responsibilities
Develop and maintain UVM-based verification environments for DDR subsystems
Create and execute detailed verification test plans
Design and implement testbench components using SystemVerilog and UVM
Develop stimulus using C/Assembly where required
Perform assertion-based verification for protocol compliance
Drive coverage-driven verification and achieve coverage closure targets
Analyze simulation results and debug functional issues using waveforms
Collaborate with design teams to understand architecture and resolve issues
Review test plans, verification strategies, and testcases
Automate verification flows using scripting languages
Work with industry-standard simulators for regression and debug
Contribute to continuous improvement of verification methodologies
Required Qualifications
Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
4–5 years of experience in SoC verification
Strong experience in DDR protocol verification (DDR4/DDR5/LPDDR)
Proven experience in coverage closure and verification sign-off
Technical Skills & Languages
SystemVerilog, Verilog
C / Assembly (for stimulus generation)
Verification Methodologies
UVM (Universal Verification Methodology)
Assertion-Based Verification (ABV)
Coverage-Driven Verification
Protocols
DDR (DDR4, DDR5, LPDDR)
Exposure to PCIe / USB / Ethernet (optional)
Tools & Simulators
Synopsys VCS
Cadence Xcelium
Mentor Questa
Debug & Analysis
Waveform debugging
Functional debugging and root cause analysis
Scripting & Automation
Python / Perl / Shell scripting
Show more Show less
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