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Senior Silicon Validation Engineer

Accepting applications

Microsoft · Bengaluru, Karnataka, India

Full-Time Principal AIC++EthernetFPGAI2C
Estimated market salary
₹43-77 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
23h ago
Category
Verification
Experience
Principal
Country
India
Overview

The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

We are looking for a Snr Validation Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISOC) Silicon team. You will be part of the Post-Silicon Validation team, driving many facets of high performance, high bandwidth designs.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

#SCHIE INDIA

Responsibilities

Lead the development of key debug tools and infrastructure for validating complex SoCs.
Define, develop, and deploy tools and methodologies for high-volume test execution and efficient silicon debugging.
Build and maintain robust infrastructure for pre-silicon SoC verification and post-silicon and FPGA validation.
Collaborate with architecture, design, verification, and partner teams to execute projects and define validation tools and methodologies for next-generation designs.
Lead silicon power-up using debug tools to diagnose failures and create stress and performance scenarios that meet test plan goals.
Participate actively in chip bring-up and develop test firmware to support multiple teams.
Coach and mentor others in your areas of expertise.
Model Microsoft’s core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgment, and Diversity and Inclusion.
Qualifications

10+ years of related technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience or internship experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
7+ years of experience in pre-silicon and post-silicon validation with a proven track record of delivering high performance Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU’s) or relevant experience.
Other Qualifications

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional Or Preferred Qualifications

Experience using scan- and JTAG-based methods, debug tools, and embedded processor debuggers.
Strong understanding of JTAG-based topologies and experience developing JTAG software tools.
Strong software development skills in C/C++, Python, with knowledge of advanced computer architecture, boot flows, FTDI, and OpenOCD.
Experience developing and driving tools and automated workflows for pre- and post-silicon validation.
Hands-on validation experience across multiple product cycles, from definition through silicon, including test planning, test development, and failure debugging.
Experience with high-speed I/O and industry-standard bus, parallel, and serial protocols, including Ethernet, PCIe, JTAG, AXI, AHB, and I2C.
Strong communication, teamwork, self-direction, and problem-solving skills.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.



This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
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